Multibank file generation (messy)

compiler/base/verilog.py

@@ -7,7 +7,6 @@
 #
 import math
 from tech import spice
-from verilog_template import verilog_template
 
 
 class verilog:
@@ -16,13 +15,19 @@ class verilog:
     This is inherited by the sram_base class.
     """
     def __init__(self):
-        self.template = verilog_template('verilog_template.v')
+        pass
-        self.template.readTemplate()
 
     def verilog_write(self, verilog_name):
         """ Write a behavioral Verilog model. """
+        self.vf = open(verilog_name, "w")
+
+        self.vf.write("// OpenRAM SRAM model\n")
+        self.vf.write("// Words: {0}\n".format(self.num_words))
+        self.vf.write("// Word size: {0}\n".format(self.word_size))
         if self.write_size:
-            self.template.setSectionRepeat('WRITE_SIZE_CMT', 1)
+            self.vf.write("// Write size: {0}\n\n".format(self.write_size))
+        else:
+            self.vf.write("\n")
 
         try:
             self.vdd_name = spice["power"]
@@ -43,8 +48,6 @@ class verilog:
         self.vf.write("`endif\n")
 
         for port in self.all_ports:
-            self.template.cloneSection("PORTS", "PORTS" + str(port))
-            
             if port in self.readwrite_ports:
                 self.vf.write("// Port {0}: RW\n".format(port))
             elif port in self.read_ports:
@@ -134,10 +137,6 @@ class verilog:
         self.vf.write("  reg [ADDR_WIDTH-1:0]  addr{0}_reg;\n".format(port))
         if port in self.write_ports:
             self.vf.write("  reg [DATA_WIDTH-1:0]  din{0}_reg;\n".format(port))
-        self.vf.write("`ifdef USE_POWER_PINS\n")
-        self.vf.write("    {},\n".format(self.vdd_name))
-        self.vf.write("    {},\n".format(self.gnd_name))
-        self.vf.write("`endif\n")
         if port in self.read_ports:
             self.vf.write("  reg [DATA_WIDTH-1:0]  dout{0};\n".format(port))
 

compiler/modules/sram.py

@@ -40,14 +40,11 @@ class sram():
 
         self.s = sram(name, sram_config)
 
-<<<<<<< HEAD
-=======
         if self.num_banks != 1:
             from sram_multibank import sram_multibank
             mb = sram_multibank(s)
             mb.verilog_write()
 
->>>>>>> 3dd65b1a (modified template engine & sram multibank class)
         self.s.create_netlist()
         if not OPTS.netlist_only:
             self.s.create_layout()

compiler/modules/sram_config.py

@@ -121,7 +121,8 @@ class sram_config:
         self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
         self.bank_addr_size = self.col_addr_size + self.row_addr_size
-        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
+        #self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
+        self.addr_size = self.bank_addr_size
         debug.info(1, "Row addr size: {}".format(self.row_addr_size)
                    + " Col addr size: {}".format(self.col_addr_size)
                    + " Bank addr size: {}".format(self.bank_addr_size))

compiler/modules/sram_multibank.py

@@ -1,16 +1,20 @@
 from template import template
 from globals import OPTS
 <<<<<<< HEAD
+<<<<<<< HEAD
 import os
 from math import ceil, log
 =======
 >>>>>>> 3dd65b1a (modified template engine & sram multibank class)
+=======
+import os
+from math import ceil, log
+>>>>>>> 22c01d7f (Multibank file generation (messy))
 
 
 class sram_multibank:
 
     def __init__(self, sram):
-<<<<<<< HEAD
         rw_ports = [i for i in sram.all_ports if i in sram.read_ports and i in sram.write_ports]
         r_ports = [i for i in sram.all_ports if i in sram.read_ports and i not in sram.write_ports]
         w_ports = [i for i in sram.all_ports if i not in sram.read_ports and i in sram.write_ports]
@@ -34,25 +38,3 @@ class sram_multibank:
         template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v")
         t = template(template_filename, self.dict)
         t.write(name)
-=======
-        dict = {
-                'module_name': OPTS.output_name, 
-                'bank_module_name': OPTS.output_name + '_1bank', 
-                'vdd': 'vdd', 
-                'gnd': 'gnd', 
-                'ports': sram.all_ports, 
-                'rw_ports': sram.readwrite_ports, 
-                'r_ports': sram.read_ports, 
-                'w_ports': sram.write_ports,
-                'banks': sram.banks,
-                'data_width': sram.word_size, 
-                'addr_width': sram.addr_size,
-                'bank_sel': list(range(sram.num_banks)),
-                'num_wmask': sram.num_wmasks
-                }
-
-    def verilog_write():
-        t = template('../sram/sram_multibank_template.v', dict)
-        t.write(OPTS.output_name + '.v')
-
->>>>>>> 3dd65b1a (modified template engine & sram multibank class)

compiler/verilogTemplate/template.py

@@ -1,72 +0,0 @@
-import re
-
-class baseSection:
-    children = []
-
-    def expand(self, dict, fd):
-        for c in self.children:
-            c.expand(dict, fd)
-
-class loopSection(baseSection):
-
-    def __init__(self, var, key):
-        self.children = []
-        self.var = var
-        self.key = key
-
-    def expand(self, dict, fd):
-        for ind in dict[self.key]:
-            dict[self.var] = ind
-            for c in self.children:
-                c.expand(dict, fd)
-        if self.var in dict:
-            del dict[self.var]
-
-class textSection(baseSection):
-    
-    def __init__(self, text):
-        self.text = text
-
-    def expand(self, dict):
-        var_re = re.compile('\{\{ (\S*) \}\}')
-        vars = var_re.finditer(self.text)
-        newText = self.text
-        for var in vars:
-            newText = newText.replace('{{ ' + var.group(1) + ' }}', str(dict[var.group(1)]))
-        print(newText, end='', file=fd)
-
-class template:
-
-    def __init__(self, template, dict):
-        self.template = template
-        self.dict = dict
-
-    def readTemplate(self):
-        lines = []
-        with open(self.template, 'r') as f:
-            lines = f.readlines()
-
-        self.baseSectionSection = baseSection()
-        sections = []
-        context = [self.baseSectionSection]
-        for_re = re.compile('\{% for (\S*) in (\S*) %\}')
-        end_re = re.compile('\{% endfor %\}')
-        for line in lines:
-            m = for_re.match(line)
-            if m:
-                section = loopSection(m.group(1), m.group(2))
-                sections.append(section)
-                context[-1].children.append(section)
-                context.append(section)
-                continue
-            if end_re.match(line):
-                context.pop()
-            else:
-                context[-1].children.append(textSection(line))
-
-    def write(self, filename):
-        fd = open(filename, 'w')
-        self.readTemplate()
-        self.baseSectionSection.expand(self.dict, fd)
-        fd.close()
-

compiler/verilog_template/template.py

@@ -13,8 +13,6 @@ class baseSection:
     It is also used as the top most section.
     """
 
-    children = []
-
     def expand(self, dict, fd):
         for c in self.children:
             c.expand(dict, fd)
@@ -25,7 +23,9 @@ class loopSection(baseSection):
     This section is for looping elements. It will repeat the children
     sections based on the key list.
     """
+
     def __init__(self, var, key):
+        self.children = []
         self.var = var
         self.key = key