Multibank file generation (messy)

compiler/modules/sram.py

@@ -40,14 +40,11 @@ class sram():
 
         self.s = sram(name, sram_config)
 
-<<<<<<< HEAD
-=======
         if self.num_banks != 1:
             from sram_multibank import sram_multibank
             mb = sram_multibank(s)
             mb.verilog_write()
 
->>>>>>> 3dd65b1a (modified template engine & sram multibank class)
         self.s.create_netlist()
         if not OPTS.netlist_only:
             self.s.create_layout()

compiler/modules/sram_config.py

@@ -121,7 +121,8 @@ class sram_config:
         self.row_addr_size = ceil(log(self.num_rows, 2))
         self.col_addr_size = int(log(self.words_per_row, 2))
         self.bank_addr_size = self.col_addr_size + self.row_addr_size
-        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
+        #self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
+        self.addr_size = self.bank_addr_size
         debug.info(1, "Row addr size: {}".format(self.row_addr_size)
                    + " Col addr size: {}".format(self.col_addr_size)
                    + " Bank addr size: {}".format(self.bank_addr_size))

compiler/modules/sram_multibank.py

@@ -1,16 +1,20 @@
 from template import template
 from globals import OPTS
 <<<<<<< HEAD
+<<<<<<< HEAD
 import os
 from math import ceil, log
 =======
 >>>>>>> 3dd65b1a (modified template engine & sram multibank class)
+=======
+import os
+from math import ceil, log
+>>>>>>> 22c01d7f (Multibank file generation (messy))
 
 
 class sram_multibank:
 
     def __init__(self, sram):
-<<<<<<< HEAD
         rw_ports = [i for i in sram.all_ports if i in sram.read_ports and i in sram.write_ports]
         r_ports = [i for i in sram.all_ports if i in sram.read_ports and i not in sram.write_ports]
         w_ports = [i for i in sram.all_ports if i not in sram.read_ports and i in sram.write_ports]
@@ -34,25 +38,3 @@ class sram_multibank:
         template_filename = os.path.join(os.path.abspath(os.environ["OPENRAM_HOME"]), "sram/sram_multibank_template.v")
         t = template(template_filename, self.dict)
         t.write(name)
-=======
-        dict = {
-                'module_name': OPTS.output_name, 
-                'bank_module_name': OPTS.output_name + '_1bank', 
-                'vdd': 'vdd', 
-                'gnd': 'gnd', 
-                'ports': sram.all_ports, 
-                'rw_ports': sram.readwrite_ports, 
-                'r_ports': sram.read_ports, 
-                'w_ports': sram.write_ports,
-                'banks': sram.banks,
-                'data_width': sram.word_size, 
-                'addr_width': sram.addr_size,
-                'bank_sel': list(range(sram.num_banks)),
-                'num_wmask': sram.num_wmasks
-                }
-
-    def verilog_write():
-        t = template('../sram/sram_multibank_template.v', dict)
-        t.write(OPTS.output_name + '.v')
-
->>>>>>> 3dd65b1a (modified template engine & sram multibank class)