mirror of https://github.com/VLSIDA/OpenRAM.git
Applied quick corner estimation to analytical delay.
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@ -235,13 +235,8 @@ class spice():
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modeling it as a resistance driving a capacitance
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modeling it as a resistance driving a capacitance
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"""
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"""
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swing_factor = abs(math.log(1-swing)) # time constant based on swing
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swing_factor = abs(math.log(1-swing)) # time constant based on swing
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proc,vdd,temp = corner
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#FIXME: type of delay is needed to know which process to use.
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proc_mult = max(self.get_process_delay_factor(proc))
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volt_mult = self.get_voltage_delay_factor(vdd)
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temp_mult = self.get_temp_delay_factor(temp)
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delay = swing_factor * r * c #c is in ff and delay is in fs
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delay = swing_factor * r * c #c is in ff and delay is in fs
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delay = delay * proc_mult * volt_mult * temp_mult
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delay = self.apply_corners_analytically(delay, corner)
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delay = delay * 0.001 #make the unit to ps
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delay = delay * 0.001 #make the unit to ps
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# Output slew should be linear to input slew which is described
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# Output slew should be linear to input slew which is described
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@ -254,6 +249,15 @@ class spice():
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slew = delay * 0.6 * 2 + 0.005 * slew
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slew = delay * 0.6 * 2 + 0.005 * slew
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return delay_data(delay = delay, slew = slew)
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return delay_data(delay = delay, slew = slew)
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def apply_corners_analytically(self, delay, corner):
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"""Multiply delay by corner factors"""
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proc,vdd,temp = corner
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#FIXME: type of delay is needed to know which process to use.
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proc_mult = max(self.get_process_delay_factor(proc))
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volt_mult = self.get_voltage_delay_factor(vdd)
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temp_mult = self.get_temp_delay_factor(temp)
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return delay * proc_mult * volt_mult * temp_mult
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def get_process_delay_factor(self, proc):
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def get_process_delay_factor(self, proc):
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"""Returns delay increase estimate based off process
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"""Returns delay increase estimate based off process
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Currently does +/-10 for fast/slow corners."""
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Currently does +/-10 for fast/slow corners."""
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@ -520,7 +520,9 @@ class sram_base(design, verilog, lef):
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wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...
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wlen_to_dout_delays = self.bank.analytical_delay(corner,slew,load,port) #port should probably be specified...
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all_delays = clk_to_wlen_delays+wlen_to_dout_delays
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all_delays = clk_to_wlen_delays+wlen_to_dout_delays
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total_delay = logical_effort.calculate_absolute_delay(all_delays)
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total_delay = logical_effort.calculate_absolute_delay(all_delays)
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total_delay = self.apply_corners_analytically(total_delay, corner)
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last_slew = .1*all_delays[-1].get_absolute_delay() #slew approximated as 10% of delay
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last_slew = .1*all_delays[-1].get_absolute_delay() #slew approximated as 10% of delay
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last_slew = self.apply_corners_analytically(last_slew, corner)
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delays[port] = self.return_delay(delay=total_delay, slew=last_slew)
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delays[port] = self.return_delay(delay=total_delay, slew=last_slew)
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return delays
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return delays
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