mirror of https://github.com/VLSIDA/OpenRAM.git
Move mux select from li to m2 in sky130
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parent
94d7000717
commit
c07e20cbe4
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@ -33,8 +33,8 @@ class single_level_column_mux_array(design.design):
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self.column_offset = column_offset
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self.column_offset = column_offset
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if "li" in layer:
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if "li" in layer:
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self.col_mux_stack = self.li_stack
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self.col_mux_stack = self.m1_stack[::-1]
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self.col_mux_stack_pitch = self.m1_pitch
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self.col_mux_stack_pitch = self.m2_pitch
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else:
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else:
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self.col_mux_stack = self.m1_stack
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self.col_mux_stack = self.m1_stack
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self.col_mux_stack_pitch = self.m1_pitch
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self.col_mux_stack_pitch = self.m1_pitch
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@ -155,7 +155,7 @@ class single_level_column_mux_array(design.design):
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self.route_bitlines()
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self.route_bitlines()
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def add_horizontal_input_rail(self):
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def add_horizontal_input_rail(self):
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""" Create address input rails on M1 below the mux transistors """
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""" Create address input rails below the mux transistors """
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for j in range(self.words_per_row):
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for j in range(self.words_per_row):
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offset = vector(0, self.route_height + (j - self.words_per_row) * self.col_mux_stack_pitch)
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offset = vector(0, self.route_height + (j - self.words_per_row) * self.col_mux_stack_pitch)
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self.add_layout_pin(text="sel_{}".format(j),
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self.add_layout_pin(text="sel_{}".format(j),
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@ -177,10 +177,10 @@ class single_level_column_mux_array(design.design):
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# use the y offset from the sel pin and the x offset from the gate
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,
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offset = vector(gate_offset.x,
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self.get_pin("sel_{}".format(sel_index)).cy())
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self.get_pin("sel_{}".format(sel_index)).cy())
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# Add the poly contact with a shift to account for the rotation
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self.add_via_stack_center(from_layer="poly",
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self.add_via_center(layers=self.poly_stack,
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to_layer=self.col_mux_stack[0],
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offset=offset,
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offset=offset,
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directions=self.via_directions)
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directions=self.via_directions)
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self.add_path("poly", [offset, gate_offset])
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self.add_path("poly", [offset, gate_offset])
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def route_bitlines(self):
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def route_bitlines(self):
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