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Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport

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This commit is contained in:
Michael Timothy Grimes
2018-02-28 04:29:38 -08:00
parent 4ea2a70a1b 01244347c1
commit bf7d846e5f
262 changed files with 4310516 additions and 4391 deletions
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compiler/tests/00_code_format_check_test.py
+2
View File
@@ -35,6 +35,8 @@ class code_format_test(openram_test):
continue
if re.search("openram.py$", code):
continue
if re.search("gen_stimulus.py$", code):
continue
errors += check_print_output(code)
# fails if there are any tabs in any files
compiler/tests/11_dff_array_test.py
+44
View File
@@ -0,0 +1,44 @@
#!/usr/bin/env python2.7
"""
Run a regresion test on a dff_array.
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
class dff_array_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
global verify
import verify
OPTS.check_lvsdrc = False
import dff_array
debug.info(2, "Testing dff_array for 3x3")
a = dff_array.dff_array(rows=3, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 1x3")
a = dff_array.dff_array(rows=1, columns=3)
self.local_check(a)
debug.info(2, "Testing dff_array for 3x1")
a = dff_array.dff_array(rows=3, columns=1)
self.local_check(a)
OPTS.check_lvsdrc = True
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()
compiler/tests/14_replica_bitline_test.py
+3 -2
View File
@@ -22,15 +22,16 @@ class replica_bitline_test(openram_test):
import replica_bitline
stages=4
fanout=4
rows=13
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,rows)
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
stages=8
rows=100
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
a = replica_bitline.replica_bitline(stages,rows)
a = replica_bitline.replica_bitline(stages,fanout,rows)
self.local_check(a)
OPTS.check_lvsdrc = True
compiler/tests/21_hspice_delay_test.py
+24 -21
View File
@@ -27,7 +27,7 @@ class timing_sram_test(openram_test):
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
import sram
import tech
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
@@ -43,32 +43,35 @@ class timing_sram_test(openram_test):
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
import tech
loads = [tech.spice["FF_in_cap"]*4]
loads = [tech.spice["msflop_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
data = d.analyze(probe_address, probe_data,slews,loads)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.0345742,
'read0_power': 0.03526189999999999,
'write0_power': 0.0270014,
'delay1': [0.0573107],
'delay0': [0.07055809999999998],
'min_period': 0.234,
'write1_power': 0.0376625,
'slew0': [0.0284344],
'slew1': [0.0189185]}
golden_data = {'leakage_power': 0.0006964536000000001,
'delay_lh': [0.0573055],
'read0_power': [0.0337812],
'read1_power': [0.032946500000000004],
'write1_power': [0.0361529],
'write0_power': [0.026179099999999997],
'slew_hl': [0.0285185],
'min_period': 0.205,
'delay_hl': [0.070554],
'slew_lh': [0.0190073]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 11.2474,
'read0_power': 11.3148,
'write0_power': 6.9064,
'delay1': [1.0298],
'delay0': [1.4102],
'min_period': 4.063,
'write1_power': 11.6964,
'slew0': [1.3118],
'slew1': [0.9816656]}
golden_data = {'leakage_power': 0.0004004581,
'delay_lh': [0.6538954],
'read0_power': [9.7622],
'read1_power': [9.589],
'write1_power': [10.2578],
'write0_power': [6.928400000000001],
'slew_hl': [0.8321625],
'min_period': 2.344,
'delay_hl': [0.9019090999999999],
'slew_lh': [0.5896232]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
compiler/tests/21_hspice_setuphold_test.py
+7 -6
View File
@@ -31,19 +31,20 @@ class timing_setup_test(openram_test):
import tech
slews = [tech.spice["rise_time"]*2]
sh = setup_hold.setup_hold()
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
sh = setup_hold.setup_hold(corner)
data = sh.analyze(slews,slews)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'setup_times_LH': [0.014648399999999999],
'hold_times_LH': [0.0024414],
'hold_times_HL': [-0.0036620999999999997],
'setup_times_HL': [0.0085449]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'setup_times_LH': [0.1000977],
'hold_times_LH': [0.020751999999999996],
'hold_times_HL': [-0.0830078],
'setup_times_HL': [0.020751999999999996]}
golden_data = {'setup_times_LH': [0.08178709999999999],
'hold_times_LH': [0.0024414],
'hold_times_HL': [-0.0646973],
'setup_times_HL': [0.0390625]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/21_ngspice_delay_test.py
+24 -21
View File
@@ -27,7 +27,7 @@ class timing_sram_test(openram_test):
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
import sram
import tech
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
@@ -41,32 +41,35 @@ class timing_sram_test(openram_test):
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
import tech
loads = [tech.spice["FF_in_cap"]*4]
loads = [tech.spice["msflop_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
data = d.analyze(probe_address, probe_data,slews,loads)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.03308298,
'read0_power': 0.03866541,
'write0_power': 0.02695139,
'delay1': [0.05840294000000001],
'delay0': [0.40787249999999997],
'min_period': 0.781,
'write1_power': 0.037257830000000006,
'slew0': [0.035826199999999996],
'slew1': [0.02059459]}
golden_data = {'leakage_power': 0.0007348262,
'delay_lh': [0.05799613],
'read0_power': [0.0384102],
'read1_power': [0.03279848],
'write1_power': [0.03693655],
'write0_power': [0.02717752],
'slew_hl': [0.03607912],
'min_period': 0.742,
'delay_hl': [0.3929995],
'slew_lh': [0.02160862]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 10.31395,
'read0_power': 10.0321,
'write0_power': 6.072756,
'delay1': [1.042564],
'delay0': [1.412224],
'min_period': 4.688,
'write1_power': 10.53758,
'slew0': [1.355812],
'slew1': [1.03401]}
golden_data = {'leakage_power': 0.00142014,
'delay_lh': [0.8018421],
'read0_power': [11.44908],
'read1_power': [11.416549999999999],
'write1_power': [11.718020000000001],
'write0_power': [8.250219],
'slew_hl': [0.8273725],
'min_period': 2.734,
'delay_hl': [1.085861],
'slew_lh': [0.5730144]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/21_ngspice_setuphold_test.py
+7 -6
View File
@@ -30,19 +30,20 @@ class timing_setup_test(openram_test):
import tech
slews = [tech.spice["rise_time"]*2]
sh = setup_hold.setup_hold()
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
sh = setup_hold.setup_hold(corner)
data = sh.analyze(slews,slews)
#print data
if OPTS.tech_name == "freepdk45":
golden_data = {'setup_times_LH': [0.01464844],
'hold_times_LH': [0.0024414059999999997],
'hold_times_HL': [-0.003662109],
'setup_times_HL': [0.008544922]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'setup_times_LH': [0.1000977],
'hold_times_LH': [0.02075195],
'hold_times_HL': [-0.08300781],
'setup_times_HL': [0.02075195]}
golden_data = {'setup_times_LH': [0.07568359],
'hold_times_LH': [0.008544922],
'hold_times_HL': [-0.05859374999999999],
'setup_times_HL': [0.03295898]}
else:
self.assertTrue(False) # other techs fail
compiler/tests/22_sram_func_test.py
+8 -7
View File
@@ -29,9 +29,9 @@ class sram_func_test(openram_test):
import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.word_size,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
s = sram.sram(word_size=1,
num_words=16,
num_banks=1,
name="sram_func_test")
OPTS.check_lvsdrc = True
@@ -43,14 +43,15 @@ class sram_func_test(openram_test):
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
d = delay.delay(s,tempspice,corner)
d.set_probe(probe_address,probe_data)
# This will exit if it doesn't find a feasible period
import tech
load = tech.spice["FF_in_cap"]*4
slew = tech.spice["rise_time"]*2
feasible_period = d.find_feasible_period(load,slew)
d.load = tech.spice["msflop_in_cap"]*4
d.slew = tech.spice["rise_time"]*2
feasible_period = d.find_feasible_period()
os.remove(tempspice)
OPTS.analytical_delay = True
compiler/tests/23_lib_sram_model_test.py
+15 -9
View File
@@ -5,7 +5,7 @@ Check the .lib file for an SRAM
import unittest
from testutils import header,openram_test
import sys,os
import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
@@ -22,22 +22,28 @@ class lib_test(openram_test):
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + "_analytical.lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname,sram=s,spfile=tempspice,use_model=True)
lib.lib(out_dir=OPTS.openram_temp, sram=s, sp_file=tempspice, use_model=True)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.15)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib","_analytical.lib")
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
self.isapproxdiff(libname,golden,0.15)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
compiler/tests/23_lib_sram_prune_test.py
+16 -10
View File
@@ -5,7 +5,7 @@ Check the .lib file for an SRAM with pruning
import unittest
from testutils import header,openram_test
import sys,os
import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
@@ -31,21 +31,27 @@ class lib_test(openram_test):
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + "_pruned.lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname,sram=s,spfile=tempspice,use_model=False)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.30)
lib.lib(out_dir=OPTS.openram_temp, sram=s, sp_file=tempspice, use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
newname = filename.replace(".lib","_pruned.lib")
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),newname)
self.isapproxdiff(libname,golden,0.15)
OPTS.analytical_delay = True
reload(characterizer)
compiler/tests/23_lib_sram_test.py
+15 -10
View File
@@ -5,7 +5,7 @@ Check the .lib file for an SRAM
import unittest
from testutils import header,openram_test
import sys,os
import sys,os,re
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
@@ -31,21 +31,26 @@ class lib_test(openram_test):
debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
s = sram.sram(word_size=2,
num_words=OPTS.num_words,
num_banks=OPTS.num_banks,
num_words=16,
num_banks=1,
name="sram_2_16_1_{0}".format(OPTS.tech_name))
OPTS.check_lvsdrc = True
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
filename = s.name + ".lib"
libname = OPTS.openram_temp + filename
lib.lib(libname=libname,sram=s,spfile=tempspice,use_model=False)
# let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.15)
lib.lib(out_dir=OPTS.openram_temp, sram=s, sp_file=tempspice, use_model=False)
# get all of the .lib files generated
files = os.listdir(OPTS.openram_temp)
nametest = re.compile("\.lib$", re.IGNORECASE)
lib_files = filter(nametest.search, files)
# and compare them with the golden model
for filename in lib_files:
libname = "{0}/{1}".format(OPTS.openram_temp,filename)
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
self.isapproxdiff(libname,golden,0.15)
OPTS.analytical_delay = True
OPTS.trim_netlist = True
compiler/tests/30_openram_test.py
+6 -1
View File
@@ -52,11 +52,16 @@ class openram_test(openram_test):
os.system(cmd)
# assert an error until we actually check a resul
for extension in ["gds", "v", "lef", "lib", "sp"]:
for extension in ["gds", "v", "lef", "sp"]:
filename = "{0}/{1}.{2}".format(out_path,out_file,extension)
debug.info(1,"Checking for file: " + filename)
self.assertEqual(os.path.exists(filename),True)
# Make sure there is any .lib file
import glob
files = glob.glob('{0}/*.lib'.format(out_path))
self.assertTrue(len(files)>0)
# grep any errors from the output
output = open("{0}/output.log".format(out_path),"r").read()
self.assertEqual(len(re.findall('ERROR',output)),0)
compiler/tests/config_20_freepdk45.py
+3
View File
@@ -3,5 +3,8 @@ num_words = 16
num_banks = 1
tech_name = "freepdk45"
process_corners = ["TT"]
supply_voltages = [1.0]
temperatures = [25]
compiler/tests/config_20_scn3me_subm.py
+3
View File
@@ -3,4 +3,7 @@ num_words = 16
num_banks = 1
tech_name = "scn3me_subm"
process_corners = ["TT"]
supply_voltages = [5.0]
temperatures = [25]
compiler/tests/golden/sram_2_16_1_freepdk45.lef
+49 -126
View File
@@ -7,11 +7,11 @@ UNITS
END UNITS
SITE MacroSite
CLASS Core ;
SIZE 21695.0 by 42337.5 ;
SIZE 24385.0 by 42337.5 ;
END MacroSite
MACRO sram_2_16_1_freepdk45
CLASS BLOCK ;
SIZE 21695.0 BY 42337.5 ;
SIZE 24385.0 BY 42337.5 ;
SYMMETRY X Y R90 ;
SITE MacroSite ;
PIN DATA[0]
@@ -4165,12 +4165,15 @@ MACRO sram_2_16_1_freepdk45
RECT 750.0 30905.0 685.0 30970.0 ;
RECT 32.5 30615.0 -32.5 31175.0 ;
RECT 1377.5 30615.0 1312.5 31175.0 ;
RECT 1377.5 39337.5 1312.5 36955.0 ;
RECT 1377.5 38217.5 1312.5 39645.0 ;
RECT 1312.5 33907.5 1025.0 33972.5 ;
RECT 1312.5 36317.5 1025.0 36382.5 ;
RECT 1312.5 36597.5 1025.0 36662.5 ;
RECT 1312.5 39007.5 1025.0 39072.5 ;
RECT 1377.5 31862.5 935.0 31927.5 ;
RECT 935.0 31862.5 230.0 31927.5 ;
RECT 20.0 35112.5 935.0 35177.5 ;
RECT 20.0 37802.5 935.0 37867.5 ;
RECT 20.0 32422.5 935.0 32487.5 ;
RECT 2005.0 33435.0 1940.0 34135.0 ;
RECT 2005.0 33627.5 1940.0 33692.5 ;
@@ -4210,11 +4213,11 @@ MACRO sram_2_16_1_freepdk45
RECT 2330.0 33497.5 2465.0 33562.5 ;
RECT 2330.0 33497.5 2465.0 33562.5 ;
RECT 2330.0 33307.5 2465.0 33372.5 ;
RECT 1312.5 39272.5 1377.5 39337.5 ;
RECT 4002.5 39272.5 4067.5 39337.5 ;
RECT 1312.5 39175.0 1377.5 39305.0 ;
RECT 1345.0 39272.5 4035.0 39337.5 ;
RECT 4002.5 39175.0 4067.5 39305.0 ;
RECT 1312.5 38152.5 1377.5 38217.5 ;
RECT 4002.5 38152.5 4067.5 38217.5 ;
RECT 1312.5 38055.0 1377.5 38185.0 ;
RECT 1345.0 38152.5 4035.0 38217.5 ;
RECT 4002.5 38055.0 4067.5 38185.0 ;
RECT 2875.0 34562.5 2690.0 34627.5 ;
RECT 4035.0 34562.5 3850.0 34627.5 ;
RECT 3917.5 34202.5 4067.5 34267.5 ;
@@ -4361,90 +4364,6 @@ MACRO sram_2_16_1_freepdk45
RECT 2722.5 37495.0 2657.5 38055.0 ;
RECT 4067.5 37495.0 4002.5 38055.0 ;
RECT 3340.0 37620.0 3475.0 37685.0 ;
RECT 2875.0 38482.5 2690.0 38547.5 ;
RECT 4035.0 38482.5 3850.0 38547.5 ;
RECT 3917.5 38122.5 4067.5 38187.5 ;
RECT 3032.5 38122.5 2657.5 38187.5 ;
RECT 3917.5 38312.5 3032.5 38377.5 ;
RECT 3032.5 38122.5 2897.5 38187.5 ;
RECT 3032.5 38312.5 2897.5 38377.5 ;
RECT 3032.5 38312.5 2897.5 38377.5 ;
RECT 3032.5 38122.5 2897.5 38187.5 ;
RECT 3917.5 38122.5 3782.5 38187.5 ;
RECT 3917.5 38312.5 3782.5 38377.5 ;
RECT 3917.5 38312.5 3782.5 38377.5 ;
RECT 3917.5 38122.5 3782.5 38187.5 ;
RECT 2942.5 38482.5 2807.5 38547.5 ;
RECT 3917.5 38482.5 3782.5 38547.5 ;
RECT 3475.0 38180.0 3340.0 38245.0 ;
RECT 3475.0 38180.0 3340.0 38245.0 ;
RECT 3440.0 38345.0 3375.0 38410.0 ;
RECT 2722.5 38055.0 2657.5 38615.0 ;
RECT 4067.5 38055.0 4002.5 38615.0 ;
RECT 3340.0 38180.0 3475.0 38245.0 ;
RECT 2875.0 39042.5 2690.0 39107.5 ;
RECT 4035.0 39042.5 3850.0 39107.5 ;
RECT 3917.5 38682.5 4067.5 38747.5 ;
RECT 3032.5 38682.5 2657.5 38747.5 ;
RECT 3917.5 38872.5 3032.5 38937.5 ;
RECT 3032.5 38682.5 2897.5 38747.5 ;
RECT 3032.5 38872.5 2897.5 38937.5 ;
RECT 3032.5 38872.5 2897.5 38937.5 ;
RECT 3032.5 38682.5 2897.5 38747.5 ;
RECT 3917.5 38682.5 3782.5 38747.5 ;
RECT 3917.5 38872.5 3782.5 38937.5 ;
RECT 3917.5 38872.5 3782.5 38937.5 ;
RECT 3917.5 38682.5 3782.5 38747.5 ;
RECT 2942.5 39042.5 2807.5 39107.5 ;
RECT 3917.5 39042.5 3782.5 39107.5 ;
RECT 3475.0 38740.0 3340.0 38805.0 ;
RECT 3475.0 38740.0 3340.0 38805.0 ;
RECT 3440.0 38905.0 3375.0 38970.0 ;
RECT 2722.5 38615.0 2657.5 39175.0 ;
RECT 4067.5 38615.0 4002.5 39175.0 ;
RECT 3340.0 38740.0 3475.0 38805.0 ;
RECT 2505.0 38187.5 2690.0 38122.5 ;
RECT 1345.0 38187.5 1530.0 38122.5 ;
RECT 1462.5 38547.5 1312.5 38482.5 ;
RECT 2347.5 38547.5 2722.5 38482.5 ;
RECT 1462.5 38357.5 2347.5 38292.5 ;
RECT 2347.5 38547.5 2482.5 38482.5 ;
RECT 2347.5 38357.5 2482.5 38292.5 ;
RECT 2347.5 38357.5 2482.5 38292.5 ;
RECT 2347.5 38547.5 2482.5 38482.5 ;
RECT 1462.5 38547.5 1597.5 38482.5 ;
RECT 1462.5 38357.5 1597.5 38292.5 ;
RECT 1462.5 38357.5 1597.5 38292.5 ;
RECT 1462.5 38547.5 1597.5 38482.5 ;
RECT 2437.5 38187.5 2572.5 38122.5 ;
RECT 1462.5 38187.5 1597.5 38122.5 ;
RECT 1905.0 38490.0 2040.0 38425.0 ;
RECT 1905.0 38490.0 2040.0 38425.0 ;
RECT 1940.0 38325.0 2005.0 38260.0 ;
RECT 2657.5 38615.0 2722.5 38055.0 ;
RECT 1312.5 38615.0 1377.5 38055.0 ;
RECT 1905.0 38425.0 2040.0 38490.0 ;
RECT 2505.0 37627.5 2690.0 37562.5 ;
RECT 1345.0 37627.5 1530.0 37562.5 ;
RECT 1462.5 37987.5 1312.5 37922.5 ;
RECT 2347.5 37987.5 2722.5 37922.5 ;
RECT 1462.5 37797.5 2347.5 37732.5 ;
RECT 2347.5 37987.5 2482.5 37922.5 ;
RECT 2347.5 37797.5 2482.5 37732.5 ;
RECT 2347.5 37797.5 2482.5 37732.5 ;
RECT 2347.5 37987.5 2482.5 37922.5 ;
RECT 1462.5 37987.5 1597.5 37922.5 ;
RECT 1462.5 37797.5 1597.5 37732.5 ;
RECT 1462.5 37797.5 1597.5 37732.5 ;
RECT 1462.5 37987.5 1597.5 37922.5 ;
RECT 2437.5 37627.5 2572.5 37562.5 ;
RECT 1462.5 37627.5 1597.5 37562.5 ;
RECT 1905.0 37930.0 2040.0 37865.0 ;
RECT 1905.0 37930.0 2040.0 37865.0 ;
RECT 1940.0 37765.0 2005.0 37700.0 ;
RECT 2657.5 38055.0 2722.5 37495.0 ;
RECT 1312.5 38055.0 1377.5 37495.0 ;
RECT 1905.0 37865.0 2040.0 37930.0 ;
RECT 2505.0 37067.5 2690.0 37002.5 ;
RECT 1345.0 37067.5 1530.0 37002.5 ;
RECT 1462.5 37427.5 1312.5 37362.5 ;
@@ -4572,24 +4491,32 @@ MACRO sram_2_16_1_freepdk45
RECT 1312.5 34695.0 1377.5 34135.0 ;
RECT 1905.0 34505.0 2040.0 34570.0 ;
RECT 3340.0 34425.0 3475.0 34490.0 ;
RECT 3340.0 36665.0 3475.0 36730.0 ;
RECT 3340.0 38905.0 3475.0 38970.0 ;
RECT 1905.0 36580.0 2040.0 36645.0 ;
RECT 3340.0 36105.0 3475.0 36170.0 ;
RECT 3340.0 37785.0 3475.0 37850.0 ;
RECT 1905.0 36020.0 2040.0 36085.0 ;
RECT 3340.0 34260.0 3475.0 34325.0 ;
RECT 1940.0 34135.0 2005.0 34340.0 ;
RECT 2657.5 34135.0 2722.5 39175.0 ;
RECT 1312.5 34135.0 1377.5 39175.0 ;
RECT 4002.5 34135.0 4067.5 39175.0 ;
RECT 2657.5 34135.0 2722.5 38055.0 ;
RECT 1312.5 34135.0 1377.5 38055.0 ;
RECT 4002.5 34135.0 4067.5 38055.0 ;
RECT 935.0 33800.0 225.0 32455.0 ;
RECT 935.0 33800.0 230.0 35145.0 ;
RECT 935.0 36490.0 230.0 35145.0 ;
RECT 935.0 36490.0 230.0 37835.0 ;
RECT 935.0 39180.0 230.0 37835.0 ;
RECT 1025.0 33907.5 140.0 33972.5 ;
RECT 1025.0 36317.5 140.0 36382.5 ;
RECT 1025.0 36597.5 140.0 36662.5 ;
RECT 1025.0 39007.5 140.0 39072.5 ;
RECT 1025.0 35112.5 140.0 35177.5 ;
RECT 1025.0 37802.5 140.0 37867.5 ;
RECT 1025.0 33767.5 140.0 33832.5 ;
RECT 1025.0 36457.5 140.0 36522.5 ;
RECT 1025.0 39147.5 140.0 39212.5 ;
RECT 1345.0 33872.5 1280.0 34007.5 ;
RECT 1345.0 36282.5 1280.0 36417.5 ;
RECT 1345.0 36562.5 1280.0 36697.5 ;
RECT 1345.0 38972.5 1280.0 39107.5 ;
RECT 1342.5 34135.0 1277.5 34270.0 ;
RECT 1377.5 31760.0 1312.5 31895.0 ;
RECT 867.5 31862.5 1002.5 31927.5 ;
@@ -4600,7 +4527,7 @@ MACRO sram_2_16_1_freepdk45
RECT 682.5 32030.0 817.5 32095.0 ;
RECT 3475.0 31335.0 3410.0 34260.0 ;
RECT 2005.0 31335.0 1940.0 32100.0 ;
RECT 20.0 31335.0 -45.0 36577.5 ;
RECT 20.0 31335.0 -45.0 39267.5 ;
RECT 2722.5 31335.0 2657.5 34135.0 ;
RECT 1377.5 31335.0 1312.5 31895.0 ;
RECT 4067.5 31335.0 4002.5 34135.0 ;
@@ -5439,29 +5366,25 @@ MACRO sram_2_16_1_freepdk45
RECT 1610.0 26387.5 1540.0 26252.5 ;
RECT 2315.0 25737.5 2245.0 25602.5 ;
RECT 2315.0 26387.5 2245.0 26252.5 ;
RECT 1380.0 31895.0 1310.0 36955.0 ;
RECT 970.0 31895.0 900.0 36645.0 ;
RECT 265.0 31895.0 195.0 36645.0 ;
RECT 1380.0 31895.0 1310.0 39645.0 ;
RECT 970.0 31895.0 900.0 39335.0 ;
RECT 265.0 31895.0 195.0 39335.0 ;
RECT 1207.5 32062.5 1137.5 32660.0 ;
RECT 785.0 32062.5 715.0 32342.5 ;
RECT 3372.5 34457.5 3442.5 34852.5 ;
RECT 3372.5 34852.5 3442.5 35412.5 ;
RECT 3372.5 35412.5 3442.5 35972.5 ;
RECT 3372.5 35972.5 3442.5 36532.5 ;
RECT 3372.5 36697.5 3442.5 37092.5 ;
RECT 3372.5 36137.5 3442.5 36532.5 ;
RECT 3372.5 36532.5 3442.5 37092.5 ;
RECT 3372.5 37092.5 3442.5 37652.5 ;
RECT 3372.5 37652.5 3442.5 38212.5 ;
RECT 3372.5 38212.5 3442.5 38772.5 ;
RECT 2655.0 38902.5 2725.0 38972.5 ;
RECT 2655.0 38422.5 2725.0 38492.5 ;
RECT 2690.0 38902.5 3407.5 38972.5 ;
RECT 2655.0 38457.5 2725.0 38937.5 ;
RECT 1972.5 38422.5 2690.0 38492.5 ;
RECT 1937.5 37897.5 2007.5 38457.5 ;
RECT 1937.5 37337.5 2007.5 37897.5 ;
RECT 2655.0 37782.5 2725.0 37852.5 ;
RECT 2655.0 37302.5 2725.0 37372.5 ;
RECT 2690.0 37782.5 3407.5 37852.5 ;
RECT 2655.0 37337.5 2725.0 37817.5 ;
RECT 1972.5 37302.5 2690.0 37372.5 ;
RECT 1937.5 36777.5 2007.5 37337.5 ;
RECT 1937.5 36217.5 2007.5 36612.5 ;
RECT 1937.5 35657.5 2007.5 36217.5 ;
RECT 1937.5 36217.5 2007.5 36777.5 ;
RECT 1937.5 35657.5 2007.5 36052.5 ;
RECT 1937.5 35097.5 2007.5 35657.5 ;
RECT 1937.5 34537.5 2007.5 35097.5 ;
RECT 3340.0 34817.5 3475.0 34887.5 ;
@@ -5470,10 +5393,6 @@ MACRO sram_2_16_1_freepdk45
RECT 3340.0 36497.5 3475.0 36567.5 ;
RECT 3340.0 37057.5 3475.0 37127.5 ;
RECT 3340.0 37617.5 3475.0 37687.5 ;
RECT 3340.0 38177.5 3475.0 38247.5 ;
RECT 3340.0 38737.5 3475.0 38807.5 ;
RECT 1905.0 38422.5 2040.0 38492.5 ;
RECT 1905.0 37862.5 2040.0 37932.5 ;
RECT 1905.0 37302.5 2040.0 37372.5 ;
RECT 1905.0 36742.5 2040.0 36812.5 ;
RECT 1905.0 36182.5 2040.0 36252.5 ;
@@ -5481,18 +5400,22 @@ MACRO sram_2_16_1_freepdk45
RECT 1905.0 35062.5 2040.0 35132.5 ;
RECT 1905.0 34502.5 2040.0 34572.5 ;
RECT 3340.0 34422.5 3475.0 34492.5 ;
RECT 3340.0 36662.5 3475.0 36732.5 ;
RECT 3340.0 38902.5 3475.0 38972.5 ;
RECT 1905.0 36577.5 2040.0 36647.5 ;
RECT 3340.0 36102.5 3475.0 36172.5 ;
RECT 3340.0 37782.5 3475.0 37852.5 ;
RECT 1905.0 36017.5 2040.0 36087.5 ;
RECT 935.0 33800.0 225.0 32455.0 ;
RECT 935.0 33800.0 230.0 35145.0 ;
RECT 935.0 36490.0 230.0 35145.0 ;
RECT 785.0 33700.0 715.0 36645.0 ;
RECT 450.0 33700.0 380.0 36645.0 ;
RECT 970.0 33700.0 900.0 36645.0 ;
RECT 265.0 33700.0 195.0 36645.0 ;
RECT 935.0 36490.0 230.0 37835.0 ;
RECT 935.0 39180.0 230.0 37835.0 ;
RECT 785.0 33700.0 715.0 39335.0 ;
RECT 450.0 33700.0 380.0 39335.0 ;
RECT 970.0 33700.0 900.0 39335.0 ;
RECT 265.0 33700.0 195.0 39335.0 ;
RECT 1347.5 33872.5 1277.5 34007.5 ;
RECT 1347.5 36282.5 1277.5 36417.5 ;
RECT 1347.5 36562.5 1277.5 36697.5 ;
RECT 1347.5 38972.5 1277.5 39107.5 ;
RECT 1345.0 34135.0 1275.0 34270.0 ;
RECT 1380.0 31760.0 1310.0 31895.0 ;
RECT 867.5 31860.0 1002.5 31930.0 ;
compiler/tests/golden/sram_2_16_1_freepdk45.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
+52 -34
View File
@@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_lib){
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@@ -7,9 +7,10 @@ library (sram_2_16_1_freepdk45_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25.000 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
@@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_lib){
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@@ -74,12 +78,18 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 918.5120625;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0.00088149731;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.04024341");
}
fall_power(scalar){
values("0.029869287");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.050563718");
}
fall_power(scalar){
values("0.055867096");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@@ -145,16 +137,16 @@ cell (sram_2_16_1_freepdk45){
"0.061, 0.062, 0.069");
}
cell_fall(CELL_TABLE) {
values("0.442, 0.443, 0.452",\
"0.442, 0.443, 0.453",\
"0.448, 0.449, 0.458");
values("0.429, 0.43, 0.439",\
"0.429, 0.431, 0.439",\
"0.435, 0.436, 0.446");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026",\
"0.013, 0.015, 0.026");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044",\
"0.029, 0.031, 0.044");
@@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@@ -304,24 +295,51 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0173748762222");
}
fall_power(scalar){
values("0.0173748762222");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0261209913889");
}
fall_power(scalar){
values("0.0261209913889");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.449");
values("0.4295");
}
fall_constraint(scalar) {
values("0.449");
values("0.4295");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.898");
values("0.859");
}
fall_constraint(scalar) {
values("0.898");
values("0.859");
}
}
}
compiler/tests/golden/sram_2_16_1_freepdk45_analytical.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
+45 -27
View File
@@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_lib){
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@@ -7,9 +7,10 @@ library (sram_2_16_1_freepdk45_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25.000 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
@@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_lib){
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@@ -74,12 +78,18 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 918.5120625;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"0.001, 0.001, 0.001");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@@ -149,12 +141,12 @@ cell (sram_2_16_1_freepdk45){
"0.123, 0.124, 0.133",\
"0.123, 0.124, 0.133");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
@@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@@ -304,6 +295,33 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
compiler/tests/golden/sram_2_16_1_freepdk45_pruned.lib → compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib
+52 -34
View File
@@ -1,4 +1,4 @@
library (sram_2_16_1_freepdk45_lib){
library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@@ -7,9 +7,10 @@ library (sram_2_16_1_freepdk45_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 1.0 ;
temperature : 25.000 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
@@ -21,6 +22,9 @@ library (sram_2_16_1_freepdk45_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 1.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@@ -45,7 +49,7 @@ library (sram_2_16_1_freepdk45_lib){
index_2("0.00125, 0.005, 0.04");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@@ -74,12 +78,18 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 918.5120625;
area : 1032.3999375;
leakage_power () {
when : "CSb";
value : 0.00088149731;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@@ -89,15 +99,6 @@ cell (sram_2_16_1_freepdk45){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0.0370166");
}
fall_power(scalar){
values("0.026622831");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@@ -126,15 +127,6 @@ cell (sram_2_16_1_freepdk45){
"-0.004, -0.004, -0.016");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0.034203045");
}
fall_power(scalar){
values("0.039377859");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@@ -145,16 +137,16 @@ cell (sram_2_16_1_freepdk45){
"0.06, 0.061, 0.067");
}
cell_fall(CELL_TABLE) {
values("0.438, 0.439, 0.449",\
"0.439, 0.44, 0.449",\
"0.445, 0.446, 0.455");
values("0.425, 0.426, 0.436",\
"0.426, 0.427, 0.436",\
"0.432, 0.433, 0.442");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.013, 0.014, 0.026",\
"0.013, 0.014, 0.026",\
"0.013, 0.015, 0.026");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043",\
"0.027, 0.029, 0.043");
@@ -168,7 +160,6 @@ cell (sram_2_16_1_freepdk45){
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@@ -304,24 +295,51 @@ cell (sram_2_16_1_freepdk45){
clock : true;
direction : input;
capacitance : 0.2091;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0158174252672");
}
fall_power(scalar){
values("0.0158174252672");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0181396362394");
}
fall_power(scalar){
values("0.0181396362394");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.449");
values("0.4295");
}
fall_constraint(scalar) {
values("0.449");
values("0.4295");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.898");
values("0.859");
}
fall_constraint(scalar) {
values("0.898");
values("0.859");
}
}
}
compiler/tests/golden/sram_2_16_1_scn3me_subm.lef
+48 -126
View File
@@ -7,11 +7,11 @@ UNITS
END UNITS
SITE MacroSite
CLASS Core ;
SIZE 277800.0 by 440700.0 ;
SIZE 305400.0 by 440700.0 ;
END MacroSite
MACRO sram_2_16_1_scn3me_subm
CLASS BLOCK ;
SIZE 277800.0 BY 440700.0 ;
SIZE 305400.0 BY 440700.0 ;
SYMMETRY X Y R90 ;
SITE MacroSite ;
PIN DATA[0]
@@ -4105,12 +4105,15 @@ MACRO sram_2_16_1_scn3me_subm
RECT 16050.0 358350.0 15150.0 359250.0 ;
RECT 8850.0 353400.0 7950.0 363000.0 ;
RECT 22650.0 353400.0 21750.0 363000.0 ;
RECT 22650.0 499050.0 21750.0 430200.0 ;
RECT 22650.0 479850.0 21750.0 457800.0 ;
RECT 21750.0 397050.0 17400.0 397950.0 ;
RECT 21750.0 420450.0 17400.0 421350.0 ;
RECT 21750.0 424650.0 17400.0 425550.0 ;
RECT 21750.0 448050.0 17400.0 448950.0 ;
RECT 22650.0 371550.0 16800.0 372450.0 ;
RECT 16800.0 371550.0 6600.0 372450.0 ;
RECT 4500.0 408600.0 16800.0 409500.0 ;
RECT 4500.0 436200.0 16800.0 437100.0 ;
RECT 4500.0 381000.0 16800.0 381900.0 ;
RECT 29250.0 397800.0 28350.0 410400.0 ;
RECT 29250.0 392850.0 28350.0 393750.0 ;
@@ -4150,11 +4153,11 @@ MACRO sram_2_16_1_scn3me_subm
RECT 32550.0 398400.0 33750.0 399600.0 ;
RECT 32550.0 398400.0 33750.0 399600.0 ;
RECT 32550.0 396000.0 33750.0 397200.0 ;
RECT 21750.0 498150.0 22650.0 499050.0 ;
RECT 49350.0 498150.0 50250.0 499050.0 ;
RECT 21750.0 496800.0 22650.0 498600.0 ;
RECT 22200.0 498150.0 49800.0 499050.0 ;
RECT 49350.0 496800.0 50250.0 498600.0 ;
RECT 21750.0 478950.0 22650.0 479850.0 ;
RECT 49350.0 478950.0 50250.0 479850.0 ;
RECT 21750.0 477600.0 22650.0 479400.0 ;
RECT 22200.0 478950.0 49800.0 479850.0 ;
RECT 49350.0 477600.0 50250.0 479400.0 ;
RECT 37950.0 417000.0 36000.0 418200.0 ;
RECT 49800.0 417000.0 47850.0 418200.0 ;
RECT 48450.0 412200.0 50250.0 413400.0 ;
@@ -4301,90 +4304,6 @@ MACRO sram_2_16_1_scn3me_subm
RECT 36450.0 468000.0 35550.0 477600.0 ;
RECT 50250.0 468000.0 49350.0 477600.0 ;
RECT 42600.0 470400.0 43800.0 471600.0 ;
RECT 37950.0 484200.0 36000.0 485400.0 ;
RECT 49800.0 484200.0 47850.0 485400.0 ;
RECT 48450.0 479400.0 50250.0 480600.0 ;
RECT 39150.0 479400.0 35550.0 480600.0 ;
RECT 48450.0 482100.0 39150.0 483000.0 ;
RECT 39150.0 479400.0 37950.0 480600.0 ;
RECT 39150.0 481800.0 37950.0 483000.0 ;
RECT 39150.0 481800.0 37950.0 483000.0 ;
RECT 39150.0 479400.0 37950.0 480600.0 ;
RECT 48450.0 479400.0 47250.0 480600.0 ;
RECT 48450.0 481800.0 47250.0 483000.0 ;
RECT 48450.0 481800.0 47250.0 483000.0 ;
RECT 48450.0 479400.0 47250.0 480600.0 ;
RECT 38550.0 484200.0 37350.0 485400.0 ;
RECT 48450.0 484200.0 47250.0 485400.0 ;
RECT 43800.0 480000.0 42600.0 481200.0 ;
RECT 43800.0 480000.0 42600.0 481200.0 ;
RECT 43650.0 482550.0 42750.0 483450.0 ;
RECT 36450.0 477600.0 35550.0 487200.0 ;
RECT 50250.0 477600.0 49350.0 487200.0 ;
RECT 42600.0 480000.0 43800.0 481200.0 ;
RECT 37950.0 493800.0 36000.0 495000.0 ;
RECT 49800.0 493800.0 47850.0 495000.0 ;
RECT 48450.0 489000.0 50250.0 490200.0 ;
RECT 39150.0 489000.0 35550.0 490200.0 ;
RECT 48450.0 491700.0 39150.0 492600.0 ;
RECT 39150.0 489000.0 37950.0 490200.0 ;
RECT 39150.0 491400.0 37950.0 492600.0 ;
RECT 39150.0 491400.0 37950.0 492600.0 ;
RECT 39150.0 489000.0 37950.0 490200.0 ;
RECT 48450.0 489000.0 47250.0 490200.0 ;
RECT 48450.0 491400.0 47250.0 492600.0 ;
RECT 48450.0 491400.0 47250.0 492600.0 ;
RECT 48450.0 489000.0 47250.0 490200.0 ;
RECT 38550.0 493800.0 37350.0 495000.0 ;
RECT 48450.0 493800.0 47250.0 495000.0 ;
RECT 43800.0 489600.0 42600.0 490800.0 ;
RECT 43800.0 489600.0 42600.0 490800.0 ;
RECT 43650.0 492150.0 42750.0 493050.0 ;
RECT 36450.0 487200.0 35550.0 496800.0 ;
RECT 50250.0 487200.0 49350.0 496800.0 ;
RECT 42600.0 489600.0 43800.0 490800.0 ;
RECT 34050.0 480600.0 36000.0 479400.0 ;
RECT 22200.0 480600.0 24150.0 479400.0 ;
RECT 23550.0 485400.0 21750.0 484200.0 ;
RECT 32850.0 485400.0 36450.0 484200.0 ;
RECT 23550.0 482700.0 32850.0 481800.0 ;
RECT 32850.0 485400.0 34050.0 484200.0 ;
RECT 32850.0 483000.0 34050.0 481800.0 ;
RECT 32850.0 483000.0 34050.0 481800.0 ;
RECT 32850.0 485400.0 34050.0 484200.0 ;
RECT 23550.0 485400.0 24750.0 484200.0 ;
RECT 23550.0 483000.0 24750.0 481800.0 ;
RECT 23550.0 483000.0 24750.0 481800.0 ;
RECT 23550.0 485400.0 24750.0 484200.0 ;
RECT 33450.0 480600.0 34650.0 479400.0 ;
RECT 23550.0 480600.0 24750.0 479400.0 ;
RECT 28200.0 484800.0 29400.0 483600.0 ;
RECT 28200.0 484800.0 29400.0 483600.0 ;
RECT 28350.0 482250.0 29250.0 481350.0 ;
RECT 35550.0 487200.0 36450.0 477600.0 ;
RECT 21750.0 487200.0 22650.0 477600.0 ;
RECT 28200.0 483600.0 29400.0 484800.0 ;
RECT 34050.0 471000.0 36000.0 469800.0 ;
RECT 22200.0 471000.0 24150.0 469800.0 ;
RECT 23550.0 475800.0 21750.0 474600.0 ;
RECT 32850.0 475800.0 36450.0 474600.0 ;
RECT 23550.0 473100.0 32850.0 472200.0 ;
RECT 32850.0 475800.0 34050.0 474600.0 ;
RECT 32850.0 473400.0 34050.0 472200.0 ;
RECT 32850.0 473400.0 34050.0 472200.0 ;
RECT 32850.0 475800.0 34050.0 474600.0 ;
RECT 23550.0 475800.0 24750.0 474600.0 ;
RECT 23550.0 473400.0 24750.0 472200.0 ;
RECT 23550.0 473400.0 24750.0 472200.0 ;
RECT 23550.0 475800.0 24750.0 474600.0 ;
RECT 33450.0 471000.0 34650.0 469800.0 ;
RECT 23550.0 471000.0 24750.0 469800.0 ;
RECT 28200.0 475200.0 29400.0 474000.0 ;
RECT 28200.0 475200.0 29400.0 474000.0 ;
RECT 28350.0 472650.0 29250.0 471750.0 ;
RECT 35550.0 477600.0 36450.0 468000.0 ;
RECT 21750.0 477600.0 22650.0 468000.0 ;
RECT 28200.0 474000.0 29400.0 475200.0 ;
RECT 34050.0 461400.0 36000.0 460200.0 ;
RECT 22200.0 461400.0 24150.0 460200.0 ;
RECT 23550.0 466200.0 21750.0 465000.0 ;
@@ -4512,22 +4431,29 @@ MACRO sram_2_16_1_scn3me_subm
RECT 21750.0 420000.0 22650.0 410400.0 ;
RECT 28200.0 416400.0 29400.0 417600.0 ;
RECT 42600.0 415200.0 43800.0 416400.0 ;
RECT 42600.0 453600.0 43800.0 454800.0 ;
RECT 42600.0 492000.0 43800.0 493200.0 ;
RECT 28200.0 452400.0 29400.0 453600.0 ;
RECT 42600.0 444000.0 43800.0 445200.0 ;
RECT 42600.0 472800.0 43800.0 474000.0 ;
RECT 28200.0 442800.0 29400.0 444000.0 ;
RECT 42600.0 412800.0 43800.0 414000.0 ;
RECT 28350.0 410400.0 29250.0 414150.0 ;
RECT 35550.0 410400.0 36450.0 496800.0 ;
RECT 21750.0 410400.0 22650.0 496800.0 ;
RECT 49350.0 410400.0 50250.0 496800.0 ;
RECT 35550.0 410400.0 36450.0 477600.0 ;
RECT 21750.0 410400.0 22650.0 477600.0 ;
RECT 49350.0 410400.0 50250.0 477600.0 ;
RECT 16800.0 395400.0 6600.0 381600.0 ;
RECT 16800.0 395400.0 6600.0 409200.0 ;
RECT 16800.0 423000.0 6600.0 409200.0 ;
RECT 16800.0 423000.0 6600.0 436800.0 ;
RECT 16800.0 450600.0 6600.0 436800.0 ;
RECT 17400.0 396900.0 6000.0 398100.0 ;
RECT 17400.0 420300.0 6000.0 421500.0 ;
RECT 17400.0 424500.0 6000.0 425700.0 ;
RECT 17400.0 447900.0 6000.0 449100.0 ;
RECT 17400.0 408600.0 6000.0 409500.0 ;
RECT 17400.0 436200.0 6000.0 437100.0 ;
RECT 22350.0 396900.0 21150.0 398100.0 ;
RECT 22350.0 420300.0 21150.0 421500.0 ;
RECT 22350.0 424500.0 21150.0 425700.0 ;
RECT 22350.0 447900.0 21150.0 449100.0 ;
RECT 22200.0 410400.0 21000.0 411600.0 ;
RECT 22800.0 370800.0 21600.0 372000.0 ;
RECT 16200.0 371400.0 17400.0 372600.0 ;
@@ -4538,7 +4464,7 @@ MACRO sram_2_16_1_scn3me_subm
RECT 12600.0 375600.0 13800.0 376800.0 ;
RECT 43800.0 362400.0 42900.0 412800.0 ;
RECT 29250.0 362400.0 28350.0 375750.0 ;
RECT 4500.0 362400.0 3600.0 425250.0 ;
RECT 4500.0 362400.0 3600.0 452850.0 ;
RECT 36450.0 362400.0 35550.0 410400.0 ;
RECT 22650.0 362400.0 21750.0 372000.0 ;
RECT 50250.0 362400.0 49350.0 410400.0 ;
@@ -5348,29 +5274,25 @@ MACRO sram_2_16_1_scn3me_subm
RECT 10800.0 288450.0 9600.0 287250.0 ;
RECT 31200.0 263100.0 30000.0 261900.0 ;
RECT 31200.0 288450.0 30000.0 287250.0 ;
RECT 22650.0 372000.0 21750.0 430200.0 ;
RECT 17250.0 372000.0 16350.0 425400.0 ;
RECT 7050.0 372000.0 6150.0 425400.0 ;
RECT 22650.0 372000.0 21750.0 457800.0 ;
RECT 17250.0 372000.0 16350.0 453000.0 ;
RECT 7050.0 372000.0 6150.0 453000.0 ;
RECT 20400.0 376200.0 19500.0 384300.0 ;
RECT 13650.0 376200.0 12750.0 381000.0 ;
RECT 42750.0 415800.0 43650.0 423000.0 ;
RECT 42750.0 423000.0 43650.0 432600.0 ;
RECT 42750.0 432600.0 43650.0 442200.0 ;
RECT 42750.0 442200.0 43650.0 451800.0 ;
RECT 42750.0 454200.0 43650.0 461400.0 ;
RECT 42750.0 444600.0 43650.0 451800.0 ;
RECT 42750.0 451800.0 43650.0 461400.0 ;
RECT 42750.0 461400.0 43650.0 471000.0 ;
RECT 42750.0 471000.0 43650.0 480600.0 ;
RECT 42750.0 480600.0 43650.0 490200.0 ;
RECT 35550.0 492150.0 36450.0 493050.0 ;
RECT 35550.0 483750.0 36450.0 484650.0 ;
RECT 36000.0 492150.0 43200.0 493050.0 ;
RECT 35550.0 484200.0 36450.0 492600.0 ;
RECT 28800.0 483750.0 36000.0 484650.0 ;
RECT 28350.0 474600.0 29250.0 484200.0 ;
RECT 28350.0 465000.0 29250.0 474600.0 ;
RECT 35550.0 472950.0 36450.0 473850.0 ;
RECT 35550.0 464550.0 36450.0 465450.0 ;
RECT 36000.0 472950.0 43200.0 473850.0 ;
RECT 35550.0 465000.0 36450.0 473400.0 ;
RECT 28800.0 464550.0 36000.0 465450.0 ;
RECT 28350.0 455400.0 29250.0 465000.0 ;
RECT 28350.0 445800.0 29250.0 453000.0 ;
RECT 28350.0 436200.0 29250.0 445800.0 ;
RECT 28350.0 445800.0 29250.0 455400.0 ;
RECT 28350.0 436200.0 29250.0 443400.0 ;
RECT 28350.0 426600.0 29250.0 436200.0 ;
RECT 28350.0 417000.0 29250.0 426600.0 ;
RECT 42600.0 422400.0 43800.0 423600.0 ;
@@ -5379,10 +5301,6 @@ MACRO sram_2_16_1_scn3me_subm
RECT 42600.0 451200.0 43800.0 452400.0 ;
RECT 42600.0 460800.0 43800.0 462000.0 ;
RECT 42600.0 470400.0 43800.0 471600.0 ;
RECT 42600.0 480000.0 43800.0 481200.0 ;
RECT 42600.0 489600.0 43800.0 490800.0 ;
RECT 28200.0 483600.0 29400.0 484800.0 ;
RECT 28200.0 474000.0 29400.0 475200.0 ;
RECT 28200.0 464400.0 29400.0 465600.0 ;
RECT 28200.0 454800.0 29400.0 456000.0 ;
RECT 28200.0 445200.0 29400.0 446400.0 ;
@@ -5390,18 +5308,22 @@ MACRO sram_2_16_1_scn3me_subm
RECT 28200.0 426000.0 29400.0 427200.0 ;
RECT 28200.0 416400.0 29400.0 417600.0 ;
RECT 42600.0 415200.0 43800.0 416400.0 ;
RECT 42600.0 453600.0 43800.0 454800.0 ;
RECT 42600.0 492000.0 43800.0 493200.0 ;
RECT 28200.0 452400.0 29400.0 453600.0 ;
RECT 42600.0 444000.0 43800.0 445200.0 ;
RECT 42600.0 472800.0 43800.0 474000.0 ;
RECT 28200.0 442800.0 29400.0 444000.0 ;
RECT 16800.0 395400.0 6600.0 381600.0 ;
RECT 16800.0 395400.0 6600.0 409200.0 ;
RECT 16800.0 423000.0 6600.0 409200.0 ;
RECT 13800.0 396000.0 12600.0 426600.0 ;
RECT 10800.0 394800.0 9600.0 425400.0 ;
RECT 17400.0 394800.0 16200.0 425400.0 ;
RECT 7200.0 394800.0 6000.0 425400.0 ;
RECT 16800.0 423000.0 6600.0 436800.0 ;
RECT 16800.0 450600.0 6600.0 436800.0 ;
RECT 13800.0 396000.0 12600.0 454200.0 ;
RECT 10800.0 394800.0 9600.0 453000.0 ;
RECT 17400.0 394800.0 16200.0 453000.0 ;
RECT 7200.0 394800.0 6000.0 453000.0 ;
RECT 22350.0 396900.0 21150.0 398100.0 ;
RECT 22350.0 420300.0 21150.0 421500.0 ;
RECT 22350.0 424500.0 21150.0 425700.0 ;
RECT 22350.0 447900.0 21150.0 449100.0 ;
RECT 22200.0 410400.0 21000.0 411600.0 ;
RECT 22800.0 370800.0 21600.0 372000.0 ;
RECT 16200.0 371400.0 17400.0 372600.0 ;
compiler/tests/golden/sram_2_16_1_scn3me_subm.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib
+121 -103
View File
@@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_lib){
library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@@ -7,9 +7,10 @@ library (sram_2_16_1_scn3me_subm_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25.000 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
@@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_lib){
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 122426.46;
area : 134589.78;
leakage_power () {
when : "CSb";
value : 0.0011563287;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@@ -89,50 +99,32 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("6.0607574");
}
fall_power(scalar){
values("3.8016626");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("6.8609238");
}
fall_power(scalar){
values("5.9579654");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
timing(){
@@ -140,24 +132,24 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.676, 0.761, 1.439",\
"0.679, 0.763, 1.443",\
"0.731, 0.813, 1.491");
values("0.473, 0.519, 0.888",\
"0.476, 0.522, 0.891",\
"0.516, 0.56, 0.928");
}
cell_fall(CELL_TABLE) {
values("0.866, 0.99, 1.98",\
"0.868, 0.993, 1.985",\
"0.92, 1.042, 2.034");
values("0.582, 0.655, 1.256",\
"0.585, 0.658, 1.259",\
"0.625, 0.697, 1.295");
}
rise_transition(CELL_TABLE) {
values("0.184, 0.333, 1.877",\
"0.185, 0.334, 1.877",\
"0.188, 0.337, 1.877");
}
fall_transition(CELL_TABLE) {
values("0.363, 0.486, 2.459",\
"0.367, 0.488, 2.459",\
"0.37, 0.495, 2.46");
rise_transition(CELL_TABLE) {
values("0.154, 0.233, 1.086",\
"0.155, 0.234, 1.086",\
"0.158, 0.237, 1.086");
}
fall_transition(CELL_TABLE) {
values("0.278, 0.359, 1.499",\
"0.278, 0.361, 1.499",\
"0.28, 0.367, 1.5");
}
}
}
@@ -168,34 +160,33 @@ cell (sram_2_16_1_scn3me_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -208,28 +199,28 @@ cell (sram_2_16_1_scn3me_subm){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -241,28 +232,28 @@ cell (sram_2_16_1_scn3me_subm){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -274,28 +265,28 @@ cell (sram_2_16_1_scn3me_subm){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -304,24 +295,51 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.91866674167");
}
fall_power(scalar){
values("4.91866674167");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.72315586111");
}
fall_power(scalar){
values("5.72315586111");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("3.125");
values("1.875");
}
fall_constraint(scalar) {
values("3.125");
values("1.875");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("6.25");
values("3.75");
}
fall_constraint(scalar) {
values("6.25");
values("3.75");
}
}
}
compiler/tests/golden/sram_2_16_1_scn3me_subm_analytical.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_analytical.lib
+45 -27
View File
@@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_lib){
library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@@ -7,9 +7,10 @@ library (sram_2_16_1_scn3me_subm_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25.000 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
@@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_lib){
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 122426.46;
area : 134589.78;
leakage_power () {
when : "CSb";
value : 0;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@@ -89,15 +99,6 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
@@ -126,15 +127,6 @@ cell (sram_2_16_1_scn3me_subm){
"0.001, 0.001, 0.001");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
@@ -149,12 +141,12 @@ cell (sram_2_16_1_scn3me_subm){
"0.556, 0.603, 1.044",\
"0.556, 0.603, 1.044");
}
rise_transition(CELL_TABLE) {
rise_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61");
}
fall_transition(CELL_TABLE) {
}
fall_transition(CELL_TABLE) {
values("0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61",\
"0.024, 0.081, 0.61");
@@ -168,7 +160,6 @@ cell (sram_2_16_1_scn3me_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
@@ -304,6 +295,33 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("0.0");
}
fall_power(scalar){
values("0.0");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
compiler/tests/golden/sram_2_16_1_scn3me_subm_pruned.lib → compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C_pruned.lib
+121 -103
View File
@@ -1,4 +1,4 @@
library (sram_2_16_1_scn3me_subm_lib){
library (sram_2_16_1_scn3me_subm_TT_5p0V_25C_lib){
delay_model : "table_lookup";
time_unit : "1ns" ;
voltage_unit : "1v" ;
@@ -7,9 +7,10 @@ library (sram_2_16_1_scn3me_subm_lib){
capacitive_load_unit(1 ,fF) ;
leakage_power_unit : "1mW" ;
pulling_resistance_unit :"1kohm" ;
operating_conditions(TT){
operating_conditions(OC){
process : 1.0 ;
voltage : 5.0 ;
temperature : 25.000 ;
temperature : 25;
}
input_threshold_pct_fall : 50.0 ;
@@ -21,6 +22,9 @@ library (sram_2_16_1_scn3me_subm_lib){
slew_lower_threshold_pct_rise : 10.0 ;
slew_upper_threshold_pct_rise : 90.0 ;
nom_voltage : 5.0;
nom_temperature : 25;
nom_process : 1.0;
default_cell_leakage_power : 0.0 ;
default_leakage_power_density : 0.0 ;
default_input_pin_cap : 1.0 ;
@@ -45,7 +49,7 @@ library (sram_2_16_1_scn3me_subm_lib){
index_2("0.0125, 0.05, 0.4");
}
default_operating_conditions : TT;
default_operating_conditions : OC;
type (DATA){
@@ -74,12 +78,18 @@ cell (sram_2_16_1_scn3me_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 122426.46;
area : 134589.78;
leakage_power () {
when : "CSb";
value : 0.0011563287;
}
cell_leakage_power : 0;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
@@ -89,50 +99,32 @@ cell (sram_2_16_1_scn3me_subm){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("5.5339993");
}
fall_power(scalar){
values("3.2697936");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("5.5897458");
}
fall_power(scalar){
values("5.460329");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
timing(){
@@ -140,24 +132,24 @@ cell (sram_2_16_1_scn3me_subm){
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.664, 0.748, 1.425",\
"0.667, 0.75, 1.429",\
"0.718, 0.8, 1.477");
values("0.458, 0.503, 0.87",\
"0.461, 0.505, 0.873",\
"0.5, 0.544, 0.911");
}
cell_fall(CELL_TABLE) {
values("0.857, 0.981, 1.971",\
"0.859, 0.984, 1.976",\
"0.911, 1.033, 2.025");
values("0.573, 0.645, 1.246",\
"0.576, 0.648, 1.249",\
"0.616, 0.687, 1.286");
}
rise_transition(CELL_TABLE) {
values("0.182, 0.331, 1.876",\
"0.183, 0.333, 1.876",\
"0.186, 0.336, 1.876");
}
fall_transition(CELL_TABLE) {
values("0.361, 0.487, 2.459",\
"0.365, 0.488, 2.459",\
"0.369, 0.496, 2.459");
rise_transition(CELL_TABLE) {
values("0.153, 0.232, 1.084",\
"0.153, 0.233, 1.084",\
"0.156, 0.236, 1.084");
}
fall_transition(CELL_TABLE) {
values("0.277, 0.36, 1.499",\
"0.277, 0.362, 1.499",\
"0.278, 0.37, 1.5");
}
}
}
@@ -168,34 +160,33 @@ cell (sram_2_16_1_scn3me_subm){
direction : input;
capacitance : 9.8242;
max_transition : 0.4;
fanout_load : 1.000000;
pin(ADDR[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -208,28 +199,28 @@ cell (sram_2_16_1_scn3me_subm){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -241,28 +232,28 @@ cell (sram_2_16_1_scn3me_subm){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -274,28 +265,28 @@ cell (sram_2_16_1_scn3me_subm){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186",\
"0.082, 0.088, 0.186");
values("0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149",\
"0.076, 0.076, 0.149");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027",\
"0.021, 0.021, 0.027");
values("0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027",\
"0.039, 0.039, 0.027");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021",\
"0.009, 0.015, 0.021");
values("-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009",\
"-0.004, -0.004, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175",\
"-0.065, -0.071, -0.175");
values("-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132",\
"-0.052, -0.059, -0.132");
}
}
}
@@ -304,24 +295,51 @@ cell (sram_2_16_1_scn3me_subm){
clock : true;
direction : input;
capacitance : 9.8242;
internal_power(){
when : "!CSb & clk & !WEb";
rise_power(scalar){
values("4.39065104738");
}
fall_power(scalar){
values("4.39065104738");
}
}
internal_power(){
when : "!CSb & !clk & WEb";
rise_power(scalar){
values("5.00353945572");
}
fall_power(scalar){
values("5.00353945572");
}
}
internal_power(){
when : "CSb";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("3.125");
values("1.875");
}
fall_constraint(scalar) {
values("3.125");
values("1.875");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("6.25");
values("3.75");
}
fall_constraint(scalar) {
values("6.25");
values("3.75");
}
}
}