mirror of https://github.com/VLSIDA/OpenRAM.git
fix pin check debug typo
This commit is contained in:
parent
8b33cb519f
commit
beef9441b7
|
|
@ -226,7 +226,7 @@ class spice():
|
||||||
subckt_line = list(filter(subckt.search, self.lvs))[0]
|
subckt_line = list(filter(subckt.search, self.lvs))[0]
|
||||||
# parses line into ports and remove subckt
|
# parses line into ports and remove subckt
|
||||||
lvs_pins = subckt_line.split(" ")[2:]
|
lvs_pins = subckt_line.split(" ")[2:]
|
||||||
debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1)
|
debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.")
|
||||||
|
|
||||||
def check_net_in_spice(self, net_name):
|
def check_net_in_spice(self, net_name):
|
||||||
"""Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""
|
"""Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue