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pbitcell vdd/gnd are on layer m1 only.

This commit is contained in:
mrg 2022-05-16 17:02:53 -07:00
parent bdd334bce9
commit bed12d2a9e
1 changed files with 11 additions and 10 deletions
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21
compiler/bitcells/pbitcell.py
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@ -99,7 +99,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.route_wordlines() self.route_wordlines()
self.route_bitlines() self.route_bitlines()
self.route_supply() self.route_supplies()
if self.replica_bitcell: if self.replica_bitcell:
self.route_rbc_short() self.route_rbc_short()
@ -424,13 +424,14 @@ class pbitcell(bitcell_base.bitcell_base):
def route_rails(self): def route_rails(self):
""" Adds gnd and vdd rails and connects them to the inverters """ """ Adds gnd and vdd rails and connects them to the inverters """
# Add rails for vdd and gnd # Add rails for vdd and gnd
gnd_ypos = self.m1_offset - self.total_ports * self.m1_nonpref_pitch gnd_ypos = self.m1_offset - self.total_ports * self.m1_nonpref_pitch
self.gnd_position = vector(0, gnd_ypos) self.gnd_position = vector(0, gnd_ypos)
self.add_rect_center(layer="m1", self.add_layout_pin_rect_center(text="gnd",
offset=self.gnd_position, layer="m1",
width=self.width) offset=self.gnd_position,
self.add_power_pin("gnd", vector(0, gnd_ypos), directions=("H", "H")) width=self.width)
vdd_ypos = self.inverter_nmos_ypos \ vdd_ypos = self.inverter_nmos_ypos \
+ self.inverter_nmos.active_height \ + self.inverter_nmos.active_height \
@ -438,10 +439,10 @@ class pbitcell(bitcell_base.bitcell_base):
+ self.inverter_pmos.active_height \ + self.inverter_pmos.active_height \
+ self.vdd_offset + self.vdd_offset
self.vdd_position = vector(0, vdd_ypos) self.vdd_position = vector(0, vdd_ypos)
self.add_rect_center(layer="m1", self.add_layout_pin_rect_center(text="vdd",
offset=self.vdd_position, layer="m1",
width=self.width) offset=self.vdd_position,
self.add_power_pin("vdd", vector(0, vdd_ypos), directions=("H", "H")) width=self.width)
def create_readwrite_ports(self): def create_readwrite_ports(self):
""" """
@ -910,7 +911,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.add_path("m2", self.add_path("m2",
[port_contact_offest, br_offset], width=contact.m1_via.height) [port_contact_offest, br_offset], width=contact.m1_via.height)
def route_supply(self): def route_supplies(self):
""" Route inverter nmos and read-access nmos to gnd. Route inverter pmos to vdd. """ """ Route inverter nmos and read-access nmos to gnd. Route inverter pmos to vdd. """
# route inverter nmos and read-access nmos to gnd # route inverter nmos and read-access nmos to gnd
nmos_contact_positions = [] nmos_contact_positions = []