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Added corner paramters to power functions. This commit does not compile (sorry)

This commit is contained in:
Hunter Nichols 2018-02-22 00:15:55 -08:00
parent d4a0f48d4f
commit beb7dad9bc
10 changed files with 34 additions and 267 deletions
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8
compiler/base/design.py
View File

@ -121,10 +121,10 @@ class design(hierarchy_spice.spice, hierarchy_layout.layout):
text+=str(i)+",\n" text+=str(i)+",\n"
return text return text
def analytical_power(self, slew, load): def analytical_power(self, vdd, temp, load):
""" Get total power of a module """ """ Get total power of a module """
#print "Getting power for ",self.name," module" #print "Getting power for ",self.name," module"
total_module_power = 0 total_module_power = self.return_power()
for inst in self.insts: # for inst in self.insts:
total_module_power += inst.mod.analytical_power(slew, load) # total_module_power += self.return_power()#inst.mod.analytical_power(vdd, temp, load)
return total_module_power return total_module_power

2
compiler/base/hierarchy_spice.py
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@ -215,7 +215,7 @@ class spice(verilog.verilog):
def generate_rc_net(self,lump_num, wire_length, wire_width): def generate_rc_net(self,lump_num, wire_length, wire_width):
return wire_spice_model(lump_num, wire_length, wire_width) return wire_spice_model(lump_num, wire_length, wire_width)
def return_power(self, dynamic, leakage): def return_power(self, dynamic=0.0, leakage=0.0):
return power_data(dynamic, leakage) return power_data(dynamic, leakage)
class delay_data: class delay_data:

7
compiler/modules/control_logic.py
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@ -97,7 +97,7 @@ class control_logic(design.design):
# GAP between main control and replica bitline # GAP between main control and replica bitline
self.replica_bitline_gap = 2*self.m2_pitch self.replica_bitline_gap = 2*self.m2_pitch
def add_modules(self): def add_modules(self):
@ -691,7 +691,10 @@ class control_logic(design.design):
def analytical_power(self, vdd, temp, load): def analytical_power(self, vdd, temp, load):
#This has yet to be fully determined. #This has yet to be fully determined.
print "Instances:" print "Instances:"
total_power = self.return_power() #empty power object
for inst in self.insts: for inst in self.insts:
print inst.name," Instance" print inst.name," Instance"
total_power += inst.mod.analytical_power(vdd, temp, load)
#currently, only return flop array power #currently, only return flop array power
return 0 return total_power

7
compiler/modules/ms_flop.py
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@ -27,8 +27,11 @@ class ms_flop(design.design):
result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"]) result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
return result return result
def analytical_power(self, slew, load = 0.0): def analytical_power(self, vdd, temp, load):
#Value taken from tech file. #Value taken from tech file.
from tech import spice from tech import spice
return spice["msflop_power"] return self.return_power()
#return spice["msflop_power"]

4
compiler/modules/ms_flop_array.py
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@ -135,5 +135,5 @@ class ms_flop_array(design.design):
def analytical_delay(self, slew, load=0.0): def analytical_delay(self, slew, load=0.0):
return self.ms.analytical_delay(slew=slew, load=load) return self.ms.analytical_delay(slew=slew, load=load)
def analytical_power(self, slew, load): # def analytical_power(self, vdd, temp, load):
return self.columns * self.ms.analytical_power(slew=slew, load=load) # return self.columns * self.ms.analytical_power(slew=slew, load=load)

11
compiler/modules/replica_bitline.py
View File

@ -344,3 +344,14 @@ class replica_bitline(design.design):
height=pin.height(), height=pin.height(),
width=pin.width()) width=pin.width())
# def analytical_power(self, vdd, temp, load):
# #This has yet to be fully determined.
# print "Instances:"
# total_power = 0
# for inst in self.insts:
# print inst.name," Instance"
# #total_power += inst.mod.analytical_power(vdd, temp, load)
# #currently, only return flop array power
# return total_power

4
compiler/pgates/pnand2.py
View File

@ -214,6 +214,6 @@ class pnand2(pgate.pgate):
c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
def analytical_power(self, slew, load=0.0): def analytical_power(self, vdd, temp, load):
#Adding a magic number until I can properly define this. #Adding a magic number until I can properly define this.
return 1 return self.return_power()

4
compiler/pgates/pnand3.py
View File

@ -234,6 +234,6 @@ class pnand3(pgate.pgate):
c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
def analytical_power(self, slew, load=0.0): def analytical_power(self, vdd, temp, load):
#Adding a magic number until I can properly define this. #Adding a magic number until I can properly define this.
return 2 return self.return_power()

3
compiler/pgates/pnor2.py
View File

@ -219,7 +219,8 @@ class pnor2(pgate.pgate):
def input_load(self): def input_load(self):
return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"] return ((self.nmos_size+self.pmos_size)/parameter["min_tx_size"])*spice["min_tx_gate_c"]
def analytical_delay(self, slew, load=0.0): def analytical_delay(self, vdd, temp, load):
r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"]) r = spice["min_tx_r"]/(self.nmos_size/parameter["min_tx_size"])
c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew) return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)

251
compiler/temp/sram_2_16_1_freepdk45_TT_10V_25C.lib
View File

@ -76,254 +76,3 @@ cell (sram_2_16_1_freepdk45){
dont_touch : true; dont_touch : true;
area : 1756.7563625; area : 1756.7563625;
bus(DATA){
bus_type : DATA;
direction : inout;
max_capacitance : 1.6728;
three_state : "!OEb & !clk";
memory_write(){
address : ADDR;
clocked_on : clk;
}
memory_read(){
address : ADDR;
}
pin(DATA[1:0]){
internal_power(){
when : "OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
internal_power(){
when : "!OEb & !clk";
rise_power(scalar){
values("0");
}
fall_power(scalar){
values("0");
}
}
timing(){
timing_sense : non_unate;
related_pin : "clk";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.167, 0.168, 0.177",\
"0.167, 0.168, 0.177",\
"0.167, 0.168, 0.177");
}
cell_fall(CELL_TABLE) {
values("0.167, 0.168, 0.177",\
"0.167, 0.168, 0.177",\
"0.167, 0.168, 0.177");
}
rise_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
}
fall_transition(CELL_TABLE) {
values("0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018",\
"0.006, 0.007, 0.018");
}
}
}
}
bus(ADDR){
bus_type : ADDR;
direction : input;
capacitance : 0.2091;
max_transition : 0.04;
fanout_load : 1.000000;
pin(ADDR[6:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
}
pin(CSb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(OEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(WEb){
direction : input;
capacitance : 0.2091;
timing(){
timing_type : setup_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk";
rise_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(clk){
clock : true;
direction : input;
capacitance : 0.2091;
timing(){
timing_type :"min_pulse_width";
related_pin : clk;
rise_constraint(scalar) {
values("0.0");
}
fall_constraint(scalar) {
values("0.0");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk;
rise_constraint(scalar) {
values("0.0");
}
fall_constraint(scalar) {
values("0.0");
}
}
}
}
}