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Update documentation for library

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Eren Dogan
2022-11-11 16:16:38 -08:00
parent e821b4a75e
commit be7c21ab64
14 changed files with 187 additions and 131 deletions
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docs/source/control_logic.md
+8 -8
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@@ -7,13 +7,13 @@ This page of the documentation explains the control logic and timing of OpenRAM.
## Table of Contents
1. [Read Timing](#read-timing)
2. [Write Timing](#write-timing)
3. [External Control Signals](#external-control-signals)
4. [Internal Control Signals](#internal-control-signals)
5. [Replica Bitline (RBL)](#replica-bitline-rbl)
6. [Internal Control Signals Diagram (Read)](#internal-control-signals-diagram-read)
7. [Internal Control Signals Diagram (Write)](#internal-control-signals-diagram-write)
8. [Clock Distribution](#clock-distribution)
1. [Write Timing](#write-timing)
1. [External Control Signals](#external-control-signals)
1. [Internal Control Signals](#internal-control-signals)
1. [Replica Bitline (RBL)](#replica-bitline-rbl)
1. [Internal Control Signals Diagram (Read)](#internal-control-signals-diagram-read)
1. [Internal Control Signals Diagram (Write)](#internal-control-signals-diagram-write)
1. [Clock Distribution](#clock-distribution)
@@ -97,4 +97,4 @@ This page of the documentation explains the control logic and timing of OpenRAM.
* This is LOW when disabled
* `gated_clk_bar = cs && clk_bar`
* This is LOW when disabled
* `gated_clk = cs && clk_buf`
* `gated_clk = cs && clk_buf`