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Update documentation for library

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Eren Dogan
2022-11-11 16:16:38 -08:00
parent e821b4a75e
commit be7c21ab64
14 changed files with 187 additions and 131 deletions
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docs/source/characterization.md
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@@ -6,19 +6,19 @@ This page of the documentation explains the characterization of OpenRAM.
## Table of Contents
1. [Characterization Overview](#characterization-overview)
2. [Characterizer Organization](#characterizer-organization)
3. [Characterization Options](#characterization-options)
4. [Characterization Measurements](#characterization-measurements)
5. [Analytical Characterization](#analytical-characterization)
6. [Multiport Characterization](#multiport-characterization)
7. [Characterizer Unit Test Use](#characterizer-unit-test-use)
8. [Functional Simulation](#functional-simulation)
9. [Power/Delay Characterization](#powerdelay-characterization)
10. [Timing Graph](#timing-graph)
11. [Graph Creation Example: Buffer](#graph-creation-example-buffer)
12. [Graph Module Exclusion](#graph-module-exclusion)
13. [Timing Measurement Checks](#timing-measurement-checks)
1. [Characterization Overview](#characterization-overview)
1. [Characterizer Organization](#characterizer-organization)
1. [Characterization Options](#characterization-options)
1. [Characterization Measurements](#characterization-measurements)
1. [Analytical Characterization](#analytical-characterization)
1. [Multiport Characterization](#multiport-characterization)
1. [Characterizer Unit Test Use](#characterizer-unit-test-use)
1. [Functional Simulation](#functional-simulation)
1. [Power/Delay Characterization](#powerdelay-characterization)
1. [Timing Graph](#timing-graph)
1. [Graph Creation Example: Buffer](#graph-creation-example-buffer)
1. [Graph Module Exclusion](#graph-module-exclusion)
1. [Timing Measurement Checks](#timing-measurement-checks)
@@ -62,9 +62,9 @@ Measures the timing/power through SPICE simulation:
## Characterization Measurements
* Characterization is performed primarily to generate tables in .lib file
* cell_rise/cell_fall - Delay of from negative clock edge to DOUT when reading a 1 or 0 respectively
* rise_transition/fall_transition - Slew of DOUT when read 1 or 0 respectively
* Setup and hold time for inputs (setup_rising, hold_rising)
* cell\_rise/cell\_fall - Delay of from negative clock edge to DOUT when reading a 1 or 0 respectively
* rise\_transition/fall\_transition - Slew of DOUT when read 1 or 0 respectively
* Setup and hold time for inputs (setup\_rising, hold\_rising)
* Total power and leakage power
* Delays and slews and intended to be independent of clock period.
* Fall delays are copied to rise delays after characterization*
@@ -175,4 +175,4 @@ In addition to measurements done for characterization. Several measurements are
* Bitline measurements - Voltage of bitlines measured the checked to have at least a 10% difference
* Bitcell Measurements - Voltage measured on internal storage of cells and check that they match the operation.
* Output voltage measurements - Output voltage (`DOUT`) checked at end of cycle so it matches operation.
* Sense Amp Enable Timing - Delay of `S_EN` should not exceed a half-period
* Sense Amp Enable Timing - Delay of `S_EN` should not exceed a half-period