mirror of https://github.com/VLSIDA/OpenRAM.git
Make both gnd rails in 6T cell from top to bottom in SCMOS. Connect in bitcell array.
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@ -116,7 +116,7 @@ class bitcell_array(design.design):
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for gnd_pin in gnd_pins:
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for gnd_pin in gnd_pins:
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# avoid duplicates by only doing even rows
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# avoid duplicates by only doing even rows
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# also skip if it isn't the pin that spans the entire cell down to the bottom
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# also skip if it isn't the pin that spans the entire cell down to the bottom
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if gnd_pin.layer=="metal2" and col%2 == 0 and gnd_pin.by()==lower_y:
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if gnd_pin.layer=="metal2" and gnd_pin.by()==lower_y:
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self.add_layout_pin(text="gnd",
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self.add_layout_pin(text="gnd",
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layer="metal2",
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layer="metal2",
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offset=gnd_pin.ll(),
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offset=gnd_pin.ll(),
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