luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Add bl/br pins to dummy array

This commit is contained in:
mrg 2020-11-12 12:38:09 -08:00
parent 190234df58
commit bdda7c4f5f
1 changed files with 10 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
compiler/modules/dummy_array.py
View File

@ -5,7 +5,6 @@
# #
from bitcell_base_array import bitcell_base_array from bitcell_base_array import bitcell_base_array
from sram_factory import factory from sram_factory import factory
from tech import cell_properties as props
from globals import OPTS from globals import OPTS
@ -77,15 +76,17 @@ class dummy_array(bitcell_base_array):
for col in range(self.column_size): for col in range(self.column_size):
for port in self.all_ports: for port in self.all_ports:
bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port]) bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
self.add_rect(layer=bl_pin.layer, self.add_layout_pin(text="bl_{0}_{1}".format(port, col),
offset=bl_pin.ll().scale(1, 0), layer=bl_pin.layer,
width=bl_pin.width(), offset=bl_pin.ll().scale(1, 0),
height=self.height) width=bl_pin.width(),
height=self.height)
br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1]) br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
self.add_rect(layer=br_pin.layer, self.add_layout_pin(text="br_{0}_{1}".format(port, col),
offset=br_pin.ll().scale(1, 0), layer=br_pin.layer,
width=br_pin.width(), offset=br_pin.ll().scale(1, 0),
height=self.height) width=br_pin.width(),
height=self.height)
wl_names = self.cell.get_all_wl_names() wl_names = self.cell.get_all_wl_names()
for row in range(self.row_size): for row in range(self.row_size):