mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-29 01:24:39 +02:00
Changes for test generation and simulation
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@@ -24,8 +24,11 @@ class rom_bank_test(openram_test):
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debug.info(1, "Testing 1kB rom cell")
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_1kB", word_size=1)
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print('wriitng file')
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a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
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self.local_check(a)
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openram.end_openram()
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# run the test from the command line
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@@ -0,0 +1,39 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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import openram
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from openram import OPTS
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from openram.sram_factory import factory
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from openram import debug
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class rom_bank_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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debug.info(1, "Testing 2kB rom cell")
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_2kB", word_size=1)
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print('wriitng file')
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a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
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self.local_check(a)
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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@@ -0,0 +1,39 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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import openram
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from openram import OPTS
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from openram.sram_factory import factory
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from openram import debug
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class rom_bank_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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debug.info(1, "Testing 4kB rom cell")
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_4kB", word_size=2)
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print('wriitng file')
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a.sp_write(OPTS.openram_temp + 'simulation_file.sp')
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self.local_check(a)
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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@@ -0,0 +1,39 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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import openram
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from openram import OPTS
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from openram.sram_factory import factory
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from openram import debug
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class rom_bank_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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openram.init_openram(config_file, is_unit_test=True)
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debug.info(1, "Testing 8kB rom cell")
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a = factory.create(module_type="rom_base_bank", strap_spacing = 8, data_file="/openram/technology/rom_data_8kB", word_size=2)
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print('wriitng file')
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a.sp_write(OPTS.openram_temp + 'simulation_file_8kB.sp')
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self.local_check(a)
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openram.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = openram.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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