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Changes for test generation and simulation

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This commit is contained in:
Jacob Walker
2023-03-30 11:30:50 -07:00
parent 89c7d50bd1
commit bbf2cd2913
12 changed files with 363 additions and 178 deletions
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compiler/modules/rom_base_array.py
+7 -3
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@@ -58,16 +58,17 @@ class rom_base_array(bitcell_base_array):
self.place_precharge()
self.place_wordline_contacts()
self.place_bitline_contacts()
self.add_boundary()
self.route_precharge()
self.add_boundary()
self.place_rails()
self.connect_taps()
def add_boundary(self):
ll = self.find_lowest_coords()
bottom_offset = - self.zero_cell.nmos.end_to_contact + self.precharge_inst.offset.y
m1_offset = self.m1_width
self.translate_all(vector(0, ll.y + 0.5 * m1_offset))
ur = self.find_highest_coords()
@@ -209,7 +210,7 @@ class rom_base_array(bitcell_base_array):
prechrg_pins.append("precharge")
prechrg_pins.append("vdd")
self.precharge_inst = self.add_inst(name="decode_array_precharge", mod=self.precharge_array)
self.precharge_inst = self.add_inst(name="bitcell_array_precharge", mod=self.precharge_array)
self.connect_inst(prechrg_pins)
@@ -390,6 +391,9 @@ class rom_base_array(bitcell_base_array):
self.add_path(layer="m1", coordinates=[start, mid1, mid2, end])
self.add_layout_pin_rect_center(text="precharge_r", layer="m1", offset=mid1)
def connect_taps(self):
array_pins = [self.tap_list[i].get_pin("poly_tap") for i in range(len(self.tap_list))]