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Removed msf data flop from bank

This commit is contained in:
Matt Guthaus 2018-04-16 16:03:46 -07:00
parent 1ba87c88f5
commit bb1ec63c4f
1 changed files with 40 additions and 77 deletions
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117
compiler/modules/bank.py
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@ -72,7 +72,9 @@ class bank(design.design):
def add_pins(self): def add_pins(self):
""" Adding pins for Bank module""" """ Adding pins for Bank module"""
for i in range(self.word_size): for i in range(self.word_size):
self.add_pin("DATA[{0}]".format(i),"INOUT") self.add_pin("DOUT[{0}]".format(i),"OUT")
for i in range(self.word_size):
self.add_pin("DIN[{0}]".format(i),"IN")
for i in range(self.addr_size): for i in range(self.addr_size):
self.add_pin("A[{0}]".format(i),"INPUT") self.add_pin("A[{0}]".format(i),"INPUT")
@ -121,7 +123,6 @@ class bank(design.design):
self.column_mux_height = 0 self.column_mux_height = 0
self.add_sense_amp_array() self.add_sense_amp_array()
self.add_write_driver_array() self.add_write_driver_array()
self.add_msf_data_in()
self.add_tri_gate_array() self.add_tri_gate_array()
# To the left of the bitcell array # To the left of the bitcell array
@ -204,11 +205,6 @@ class bank(design.design):
self.row_decoder = self.mod_decoder(rows=self.num_rows) self.row_decoder = self.mod_decoder(rows=self.num_rows)
self.add_mod(self.row_decoder) self.add_mod(self.row_decoder)
self.msf_data_in = self.mod_ms_flop_array(name="msf_data_in",
columns=self.num_cols,
word_size=self.word_size)
self.add_mod(self.msf_data_in)
self.tri_gate_array = self.mod_tri_gate_array(columns=self.num_cols, self.tri_gate_array = self.mod_tri_gate_array(columns=self.num_cols,
word_size=self.word_size) word_size=self.word_size)
self.add_mod(self.tri_gate_array) self.add_mod(self.tri_gate_array)
@ -306,7 +302,7 @@ class bank(design.design):
temp = [] temp = []
for i in range(self.word_size): for i in range(self.word_size):
temp.append("data_in[{0}]".format(i)) temp.append("DIN[{0}]".format(i))
for i in range(self.word_size): for i in range(self.word_size):
if (self.words_per_row == 1): if (self.words_per_row == 1):
temp.append("bl[{0}]".format(i)) temp.append("bl[{0}]".format(i))
@ -317,37 +313,19 @@ class bank(design.design):
temp.extend([self.prefix+"w_en", "vdd", "gnd"]) temp.extend([self.prefix+"w_en", "vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)
def add_msf_data_in(self):
""" data_in flip_flop """
y_offset= self.sense_amp_array.height + self.column_mux_height \
+ self.write_driver_array.height + self.msf_data_in.height
self.msf_data_in_inst=self.add_inst(name="data_in_flop_array",
mod=self.msf_data_in,
offset=vector(0,y_offset).scale(-1,-1))
temp = []
for i in range(self.word_size):
temp.append("DATA[{0}]".format(i))
for i in range(self.word_size):
temp.append("data_in[{0}]".format(i))
temp.append("data_in_bar[{0}]".format(i))
temp.extend([self.prefix+"clk_buf_bar", "vdd", "gnd"])
self.connect_inst(temp)
def add_tri_gate_array(self): def add_tri_gate_array(self):
""" data tri gate to drive the data bus """ """ data tri gate to drive the data bus """
y_offset = self.sense_amp_array.height+self.column_mux_height \ y_offset = self.sense_amp_array.height+self.column_mux_height \
+ self.write_driver_array.height + self.msf_data_in.height + self.write_driver_array.height + self.tri_gate_array.height
self.tri_gate_array_inst=self.add_inst(name="tri_gate_array", self.tri_gate_array_inst=self.add_inst(name="tri_gate_array",
mod=self.tri_gate_array, mod=self.tri_gate_array,
offset=vector(0,y_offset).scale(-1,-1), offset=vector(0,y_offset).scale(-1,-1))
mirror="MX")
temp = [] temp = []
for i in range(self.word_size): for i in range(self.word_size):
temp.append("data_out[{0}]".format(i)) temp.append("data_out[{0}]".format(i))
for i in range(self.word_size): for i in range(self.word_size):
temp.append("DATA[{0}]".format(i)) temp.append("DOUT[{0}]".format(i))
temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"]) temp.extend([self.prefix+"tri_en", self.prefix+"tri_en_bar", "vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)
@ -463,7 +441,6 @@ class bank(design.design):
self.precharge_array_inst, self.precharge_array_inst,
self.sense_amp_array_inst, self.sense_amp_array_inst,
self.write_driver_array_inst, self.write_driver_array_inst,
self.msf_data_in_inst,
self.tri_gate_array_inst, self.tri_gate_array_inst,
self.row_decoder_inst, self.row_decoder_inst,
self.wordline_driver_inst] self.wordline_driver_inst]
@ -599,53 +576,48 @@ class bank(design.design):
""" Routing of sense amp output to tri_gate input """ """ Routing of sense amp output to tri_gate input """
for i in range(self.word_size): for i in range(self.word_size):
# Connection of data_out of sense amp to data_in
tri_gate_in = self.tri_gate_array_inst.get_pin("in[{}]".format(i)).uc()
# Connection of data_out of sense amp to data_ in of msf_data_out
tri_gate_in = self.tri_gate_array_inst.get_pin("in[{}]".format(i)).bc()
sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).bc() sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).bc()
# if we need a bend or not self.add_path("metal2",[sa_data_out,tri_gate_in])
if tri_gate_in.x-sa_data_out.x>self.m2_pitch: # # if we need a bend or not
# We'll connect to the bottom of the SA pin # if tri_gate_in.x-sa_data_out.x>self.m2_pitch:
bendX = sa_data_out.x # # We'll connect to the bottom of the SA pin
else: # bendX = sa_data_out.x
# We'll connect to the left of the SA pin # else:
sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).lc() # # We'll connect to the left of the SA pin
bendX = tri_gate_in.x - 3*self.m3_width # sa_data_out = self.sense_amp_array_inst.get_pin("data[{}]".format(i)).lc()
# bendX = tri_gate_in.x - 3*self.m3_width
bendY = tri_gate_in.y - 2*self.m2_width # bendY = tri_gate_in.y - 2*self.m2_width
# Connection point of M2 and M3 paths, below the tri gate and # # Connection point of M2 and M3 paths, below the tri gate and
# to the left of the tri gate input # # to the left of the tri gate input
bend = vector(bendX, bendY) # bend = vector(bendX, bendY)
# Connect an M2 path to the gate # # Connect an M2 path to the gate
mid3 = [tri_gate_in.x, bendY] # guarantee down then left # mid3 = [tri_gate_in.x, bendY] # guarantee down then left
self.add_path("metal2", [bend, mid3, tri_gate_in]) # self.add_path("metal2", [bend, mid3, tri_gate_in])
# connect up then right to sense amp # # connect up then right to sense amp
mid1 = vector(bendX,sa_data_out.y) # mid1 = vector(bendX,sa_data_out.y)
self.add_path("metal3", [bend, mid1, sa_data_out]) # self.add_path("metal3", [bend, mid1, sa_data_out])
offset = bend - vector([0.5*drc["minwidth_metal3"]] * 2) # offset = bend - vector([0.5*drc["minwidth_metal3"]] * 2)
self.add_via(("metal2", "via2", "metal3"),offset) # self.add_via(("metal2", "via2", "metal3"),offset)
def route_tri_gate_out(self): def route_tri_gate_out(self):
""" Metal 3 routing of tri_gate output data """ """ Metal 3 routing of tri_gate output data """
for i in range(self.word_size): for i in range(self.word_size):
tri_gate_out_position = self.tri_gate_array_inst.get_pin("out[{}]".format(i)).ul() data_pin = self.tri_gate_array_inst.get_pin("out[{}]".format(i))
data_line_position = vector(tri_gate_out_position.x, self.min_y_offset) self.add_layout_pin_rect_center(text="DATA[{}]".format(i),
self.add_via(("metal2", "via2", "metal3"), data_line_position) layer="metal2",
self.add_rect(layer="metal3", offset=data_pin.center(),
offset=data_line_position, height=data_pin.height(),
width=drc["minwidth_metal3"], width=data_pin.width()),
height=tri_gate_out_position.y - self.min_y_offset)
self.add_layout_pin(text="DATA[{}]".format(i),
layer="metal2",
offset=data_line_position,
height=2*self.m2_width)
def route_row_decoder(self): def route_row_decoder(self):
""" Routes the row decoder inputs and supplies """ """ Routes the row decoder inputs and supplies """
@ -757,14 +729,6 @@ class bank(design.design):
layer="metal2", layer="metal2",
offset=br_pin.ll()) offset=br_pin.ll())
# Add the data input names to the data flop output
for i in range(self.word_size):
dout_name = "dout[{}]".format(i)
dout_pin = self.msf_data_in_inst.get_pin(dout_name)
self.add_label(text="data_in[{}]".format(i),
layer="metal2",
offset=dout_pin.ll())
# Add the data output names to the sense amp output # Add the data output names to the sense amp output
for i in range(self.word_size): for i in range(self.word_size):
data_name = "data[{}]".format(i) data_name = "data[{}]".format(i)
@ -782,7 +746,6 @@ class bank(design.design):
# Connection from the central bus to the main control block crosses # Connection from the central bus to the main control block crosses
# pre-decoder and this connection is in metal3 # pre-decoder and this connection is in metal3
connection = [] connection = []
connection.append((self.prefix+"clk_buf_bar", self.msf_data_in_inst.get_pin("clk").lc()))
connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc())) connection.append((self.prefix+"tri_en_bar", self.tri_gate_array_inst.get_pin("en_bar").lc()))
connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc())) connection.append((self.prefix+"tri_en", self.tri_gate_array_inst.get_pin("en").lc()))
connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst.get_pin("en").lc())) connection.append((self.prefix+"clk_buf_bar", self.precharge_array_inst.get_pin("en").lc()))
@ -814,7 +777,7 @@ class bank(design.design):
# Route the vdd rails to the RIGHT # Route the vdd rails to the RIGHT
modules = [self.precharge_array_inst, self.sense_amp_array_inst, modules = [self.precharge_array_inst, self.sense_amp_array_inst,
self.write_driver_array_inst, self.msf_data_in_inst, self.write_driver_array_inst,
self.tri_gate_array_inst] self.tri_gate_array_inst]
for inst in modules: for inst in modules:
for vdd_pin in inst.get_pins("vdd"): for vdd_pin in inst.get_pins("vdd"):
@ -858,7 +821,7 @@ class bank(design.design):
""" Route gnd rails""" """ Route gnd rails"""
# Route the gnd rails to the RIGHT # Route the gnd rails to the RIGHT
# precharge is connected by abutment # precharge is connected by abutment
modules = [ self.tri_gate_array_inst, self.sense_amp_array_inst, self.msf_data_in_inst, self.write_driver_array_inst] modules = [ self.tri_gate_array_inst, self.sense_amp_array_inst, self.write_driver_array_inst]
for inst in modules: for inst in modules:
for gnd_pin in inst.get_pins("gnd"): for gnd_pin in inst.get_pins("gnd"):
if gnd_pin.layer != "metal1": if gnd_pin.layer != "metal1":