luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Allow overriding the cell size layer name.

This commit is contained in:
Tim 'mithro' Ansell 2020-11-02 10:03:52 -08:00
parent 232f754c73
commit bb164d915d
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/bitcells/bitcell.py
View File

@ -35,6 +35,8 @@ class bitcell(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar'] storage_nets = ['Q', 'Q_bar']
cell_size_layer = "boundary"
def __init__(self, name=""): def __init__(self, name=""):
if not name: if not name:
name = self.name name = self.name
@ -44,7 +46,7 @@ class bitcell(bitcell_base.bitcell_base):
(width, height) = utils.get_libcell_size(name, (width, height) = utils.get_libcell_size(name,
GDS["unit"], GDS["unit"],
layer["boundary"]) layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names, pin_map = utils.get_libcell_pins(self.pin_names,
name, name,
GDS["unit"]) GDS["unit"])