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Update timing to be from NEGATIVE edge in docs. Update sense amplifier to have PMOS for bitline isolation.

This commit is contained in:
Matt Guthaus 2018-02-12 17:08:01 -08:00
parent 72b3072e3f
commit bad24f9c8a
10 changed files with 473 additions and 493 deletions
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@ -407,13 +407,10 @@ bitlines are automatically pitch-matched to the bitcell array.
\subsection{Sense Amplifier} \subsection{Sense Amplifier}
\label{sec:senseamp} \label{sec:senseamp}
The sense amplifier is used to sense the difference between the The sense amplifier is used to sense the difference between the
bitline and bitline bar while a read operation is performed. The bitline and bitline bar while a read operation is performed.
sense amp is necessary to recover the signals from the bitlines The sense amplifier also includes two PMOS transistors for bitline
because they do not experience full voltage swing. As the size of the isolation to speed-up read operations. The schematic for the sense amp is shown in
memory array grows, the load of the bitlines increases and the voltage Figure~\ref{fig:sense_amp}.
swing is limited by the small memory cell driving this large load. A
differential sense amplifier is used to``sense'' the small voltage
difference between the bitlines.
\begin{figure}[h!] \begin{figure}[h!]
\centering \centering
@ -422,33 +419,47 @@ difference between the bitlines.
\label{fig:sense_amp} \label{fig:sense_amp}
\end{figure} \end{figure}
The schematic for the sense amp is shown in During address decoding (while the wordline is not asserted), the sense
Figure~\ref{fig:sense_amp}. The sense amplifier is enable by the SCLK amplifier is disabled and the bitlines are precharged to vdd by the
signal, which initiates the read operation. Before the sense precharge unit. The two PMOS transistors also connect the bitlines to the sense amplifier.
amplifier is enable, the bitlines are precharged to Vdd by the
precharge unit. When the sense amp is enabled, one of the bitlines The en signal comes from the control logic (Section~\ref{sec:control})
experiences a voltage drop based on the value stored in the memory including the timing and replica bitline (Section~\ref{sec:RBL}). It
cell. If a zero is stored, the bitline voltage drops. If a one is is only enabled after sufficient swing is seen on the bitlines so that
stored, the bitline bar voltage drops. The output signal is then the value can be accurately sensed.
The sense amplifier is enabled by the en signal, which initiates the
read operation, and also isolates the sense amplifier from the
bitlines. This allows the sense amplifier to drive a smaller
capacitance rather than the whole bitline. At this time, the footer
transistor is also enabled which allows the sense amplifier to use
feedback to sense the bitline differential voltage.
When the sense amp is enabled, one of the bitlines experiences a
voltage drop based on the value stored in the memory cell. If a zero
is stored, the bitline voltage drops. If a one is stored, the bitline
bar voltage drops. The output signal is then
taken to a true logic level and latched for output to the data bus. taken to a true logic level and latched for output to the data bus.
In OpenRAM, the sense amplifier is a libray cell. The associated In OpenRAM, the sense amplifier is a libray cell. The associated
layout and spice netlist can be found in the \verb|gds_lib| and \verb|sp_lib| in layout and spice netlist can be found in the \verb|gds_lib| and
the FreePDK45 directory. The \verb|sense_amp| class in \verb|sense_amp.py| \verb|sp_lib| in the technology directory. The sense\_amp class in
instantiates a single instance of the sense amp library cell. The \verb|modules/sense_amp.py| is a single instance of the sense amp
\verb|sense_amp_array| class handles the tiling of the sense amps cells. library cell.
One sense amp cell is needed per data bit and the sense amp cells need
to be appropriately spaced so that they can hook up to the column mux
bitline pairs. The spacing is determined based on the number of words
per row in the memory array. Instances are added and then Vdd, Gnd
and SCLK rails that span the entire width of the array are drawn using
the add\_rect() function.
We chose to leave the sense amp as a libray cell so that custom
The sense\_amp\_array class in \verb|modules/sense_amp_array.py|
handles the tiling of the sense amps cells. One sense amp cell is
needed per data bit and the sense amp cells need to be appropriately
spaced so that they can hook up to the column mux bitline pairs. The
spacing is determined based on the number of words per row in the
memory array.
The sense amp is a library cell so that custom
amplifier designs could be swapped into the memory as needed. The two amplifier designs could be swapped into the memory as needed. The two
major things that need to be considered while designing the sense major things that need to be considered while designing the sense
amplifier cell are the size of the cell and the bitline/input pitches. amplifier cell are the size of the cell and the bitline/input pitches.
Optimally, the cell should be no larger than the 6T cell so that it Optimally, the cell should be no wider than the 6T cell so that it
abuts to the column mux and no extra routing or space is needed. abuts to the column mux and no extra routing or space is needed.
Also, the bitline inputs of the sense amp need to line up with the Also, the bitline inputs of the sense amp need to line up with the
outputs of the write driver. In the current version of OpenRAM, the outputs of the write driver. In the current version of OpenRAM, the
@ -460,6 +471,7 @@ connect the write driver to the column mux without any extra routing.
\subsection{Write Driver} \subsection{Write Driver}
\label{sec:writedriver} \label{sec:writedriver}
The write driver is used to drive the input signal into the memory The write driver is used to drive the input signal into the memory
cell during a write operation. It can be seen in cell during a write operation. It can be seen in
Figure~\ref{fig:write_driver} that the write driver consists of two Figure~\ref{fig:write_driver} that the write driver consists of two

8
docs/timing.tex
View File

@ -10,7 +10,7 @@ Top-Level Signals:
\setlength{\itemsep}{0pt} \setlength{\itemsep}{0pt}
\item ADDR - address bus. \item ADDR - address bus.
\item DATA - bi-directional data bus. \item DATA - bi-directional data bus.
\item CLK - the global clock. \item clk - the global clock.
\item OEb - active low output enable. \item OEb - active low output enable.
\item CSb - active low chip select. \item CSb - active low chip select.
\item WEb - active low write enable. \item WEb - active low write enable.
@ -34,7 +34,7 @@ The main timing considerations for an SRAM are:
\item Setup Time - time an input needs to be stable before the positive/negative clock edge. \item Setup Time - time an input needs to be stable before the positive/negative clock edge.
\item Hold Time - time an input needs to stay valid after the positive/negative clock edge. \item Hold Time - time an input needs to stay valid after the positive/negative clock edge.
\item Minimun Cycle Time - time inbetween subsequent memory operations. \item Minimun Cycle Time - time inbetween subsequent memory operations.
\item Memory Read Time - time from positive clock edge until valid data appears on the data bus. \item Memory Read Time - time from negative clock edge until valid data appears on the data bus.
\item Memory Write Time - time from negative clock edge until data has been driven into a memory cell. \item Memory Write Time - time from negative clock edge until data has been driven into a memory cell.
\end{itemize} \end{itemize}
@ -66,9 +66,9 @@ Read Operation:
\end{enumerate} \end{enumerate}
\item On the falling edge of the clock (CLK): \item On the falling edge of the clock (CLK):
\begin{enumerate} \begin{enumerate}
\item Word line has been asserted, the value stored in the memory cells pulls down one of the bitlines (BL if a 0 is stored, BL\_bar if a 1 is stored). \item Word line is driven onto the bitlines, the value stored in the memory cells pulls down one of the bitlines (bl if a 0 is stored, br if a 1 is stored).
\item s\_en enables the sense amplifier which senses the voltage difference of the bit lines, produces the output and keeps the value in its latch circuitry. \item s\_en enables the sense amplifier which senses the voltage difference of the bit lines, produces the output and keeps the value in its latch circuitry.
\item Tri-gate enables and put the output data on data bus. Data remains valid on the data bus for a complete clock cycle. \item Tri-gate drives (tri\_en and tri\_en\_bar) the output data on data bus. Data remains valid on the data bus for a complete clock cycle.
\end{enumerate} \end{enumerate}
\end{enumerate} \end{enumerate}