mirror of https://github.com/VLSIDA/OpenRAM.git
Fix control logic routing.
This commit is contained in:
Matt Guthaus
parent
d36f14b408
commit
bac684a82a
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@ -343,11 +343,11 @@ class control_logic(design.design):
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"]
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"]
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elif self.port_type == "r":
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self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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else:
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self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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self.internal_bus_list = ["rbl_bl_delay_bar", "rbl_bl_delay", "gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
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@ -381,6 +381,7 @@ class control_logic(design.design):
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self.create_gated_clk_buf_row()
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self.create_wlen_row()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_rbl_delay_row()
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self.create_wen_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.create_sen_row()
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@ -418,6 +419,9 @@ class control_logic(design.design):
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row += 1
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self.place_pen_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_rbl_delay_row(row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.place_sen_row(row)
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row += 1
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@ -442,6 +446,7 @@ class control_logic(design.design):
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self.route_dffs()
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self.route_wlen()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.route_rbl_delay()
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self.route_wen()
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.route_sen()
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@ -469,7 +474,18 @@ class control_logic(design.design):
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self.delay_inst.place(offset, mirror="MY")
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def route_delay(self):
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out_pos = self.delay_inst.get_pin("out").bc()
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# Connect to the rail level with the vdd rail
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# Use pen since it is in every type of control logic
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vdd_ypos = self.p_en_bar_nand_inst.get_pin("vdd").by()
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in_pos = vector(self.rail_offsets["rbl_bl_delay"].x,vdd_ypos)
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mid1 = vector(out_pos.x,in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[out_pos, mid1, in_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=in_pos)
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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@ -481,12 +497,9 @@ class control_logic(design.design):
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self.connect_inst(["clk","clk_buf","vdd","gnd"])
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def place_clk_buf_row(self,row):
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""" Place the multistage clock buffer below the control flops """
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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x_offset = self.control_x_offset
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offset = vector(x_off,y_off)
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self.clk_buf_inst.place(offset, mirror)
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x_offset = self.place_util(self.clk_buf_inst, x_offset, row)
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self.row_end_inst.append(self.clk_buf_inst)
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@ -523,17 +536,10 @@ class control_logic(design.design):
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self.connect_inst(["cs","clk_bar","gated_clk_bar","vdd","gnd"])
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def place_gated_clk_bar_row(self,row):
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""" Place the gated clk logic below the control flops """
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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x_offset = self.control_x_offset
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offset = vector(x_off,y_off)
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self.clk_bar_inst.place(offset, mirror)
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x_off += self.inv.width
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offset = vector(x_off,y_off)
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self.gated_clk_bar_inst.place(offset, mirror)
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x_offset = self.place_util(self.clk_bar_inst, x_offset, row)
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x_offset = self.place_util(self.gated_clk_bar_inst, x_offset, row)
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self.row_end_inst.append(self.gated_clk_bar_inst)
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@ -567,12 +573,9 @@ class control_logic(design.design):
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self.connect_inst(["clk_buf", "cs","gated_clk_buf","vdd","gnd"])
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def place_gated_clk_buf_row(self,row):
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""" Place the gated clk logic below the control flops """
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off,y_off)
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self.gated_clk_buf_inst.place(offset, mirror)
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.gated_clk_buf_inst, x_offset, row)
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self.row_end_inst.append(self.gated_clk_buf_inst)
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@ -594,11 +597,9 @@ class control_logic(design.design):
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self.connect_inst(["gated_clk_bar", "wl_en", "vdd", "gnd"])
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def place_wlen_row(self, row):
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off, y_off)
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self.wl_en_inst.place(offset, mirror)
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.wl_en_inst, x_offset, row)
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self.row_end_inst.append(self.wl_en_inst)
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@ -609,29 +610,32 @@ class control_logic(design.design):
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_pen_row(self):
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self.p_en_bar_inst=self.add_inst(name="nand_p_en_bar",
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mod=self.nand2)
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self.p_en_bar_nand_inst=self.add_inst(name="nand_p_en_bar",
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mod=self.nand2)
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self.connect_inst(["gated_clk_buf", "rbl_bl_delay", "p_en_bar_unbuf", "vdd", "gnd"])
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self.p_en_bar_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.p_en_bar_driver_inst=self.add_inst(name="buf_p_en_bar",
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mod=self.p_en_bar_driver)
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self.connect_inst(["p_en_bar_unbuf", "p_en_bar", "vdd", "gnd"])
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def place_pen_row(self,row):
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off,y_off)
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self.p_en_bar_inst.place(offset, mirror)
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x_offset = self.control_x_offset
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self.row_end_inst.append(self.p_en_bar_inst)
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x_offset = self.place_util(self.p_en_bar_nand_inst, x_offset, row)
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x_offset = self.place_util(self.p_en_bar_driver_inst, x_offset, row)
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self.row_end_inst.append(self.p_en_bar_driver_inst)
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def route_pen(self):
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in_map = zip(["A"], ["gated_clk_buf"])
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self.connect_vertical_bus(in_map, self.p_en_bar_inst, self.rail_offsets)
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in_map = zip(["A", "B"], ["gated_clk_buf", "rbl_bl_delay"])
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self.connect_vertical_bus(in_map, self.p_en_bar_nand_inst, self.rail_offsets)
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out_pos = self.p_en_bar_nand_inst.get_pin("Z").rc()
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in_pos = self.p_en_bar_driver_inst.get_pin("A").lc()
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mid1 = vector(out_pos.x,in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[out_pos, mid1,in_pos])
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self.connect_output(self.p_en_bar_inst, "Z", "p_en_bar")
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self.connect_output(self.p_en_bar_driver_inst, "Z", "p_en_bar")
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def create_sen_row(self):
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""" Create the sense enable buffer. """
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@ -646,15 +650,9 @@ class control_logic(design.design):
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def place_sen_row(self,row):
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"""
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The sense enable buffer gets placed to the far right of the
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row.
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"""
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x_off = self.control_x_offset
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(y_off,mirror)=self.get_offset(row)
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x_offset = self.control_x_offset
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offset = vector(x_off, y_off)
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self.s_en_gate_inst.place(offset, mirror)
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x_offset = self.place_util(self.s_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.s_en_gate_inst)
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@ -666,23 +664,41 @@ class control_logic(design.design):
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else:
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input_name = "cs_bar"
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sen_map = zip(["B"], [input_name])
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sen_map = zip(["A", "B"], ["rbl_bl_delay", input_name])
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self.connect_vertical_bus(sen_map, self.s_en_gate_inst, self.rail_offsets)
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out_pos = self.delay_inst.get_pin("out").bc()
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in_pos = self.s_en_gate_inst.get_pin("A").lc()
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mid1 = vector(out_pos.x,in_pos.y)
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self.add_wire(("metal1","via1","metal2"),[out_pos, mid1,in_pos])
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self.connect_output(self.s_en_gate_inst, "Z", "s_en")
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def create_wen_row(self):
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def create_rbl_delay_row(self):
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self.rbl_bl_delay_inv_inst = self.add_inst(name="rbl_bl_delay_inv",
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mod=self.inv)
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self.connect_inst(["rbl_bl_delay", "rbl_bl_delay_bar", "vdd", "gnd"])
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def place_rbl_delay_row(self,row):
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.rbl_bl_delay_inv_inst, x_offset, row)
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self.row_end_inst.append(self.rbl_bl_delay_inv_inst)
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def route_rbl_delay(self):
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# Connect from delay line
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# Connect to rail
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rbl_map = zip(["Z"], ["rbl_bl_delay_bar"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=self.rbl_bl_delay_inv_inst.get_pin("Z").center())
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rbl_map = zip(["A"], ["rbl_bl_delay"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets)
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def create_wen_row(self):
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# input: we (or cs) output: w_en
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if self.port_type == "rw":
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input_name = "we"
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@ -697,11 +713,9 @@ class control_logic(design.design):
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def place_wen_row(self,row):
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x_off = self.ctrl_dff_inst.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off, y_off)
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self.w_en_gate_inst.place(offset, mirror)
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x_offset = self.control_x_offset
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x_offset = self.place_util(self.w_en_gate_inst, x_offset, row)
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self.row_end_inst.append(self.w_en_gate_inst)
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@ -712,7 +726,7 @@ class control_logic(design.design):
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# No we for write-only reports, so use cs
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input_name = "cs"
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wen_map = zip(["A", "B"], [input_name, "gated_clk_bar"])
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wen_map = zip(["A", "B", "C"], [input_name, "rbl_bl_delay_bar", "gated_clk_bar"])
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self.connect_vertical_bus(wen_map, self.w_en_gate_inst, self.rail_offsets)
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self.connect_output(self.w_en_gate_inst, "Z", "w_en")
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@ -791,9 +805,8 @@ class control_logic(design.design):
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self.add_power_pin("gnd", pin_loc)
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self.add_path("metal1", [row_loc, pin_loc])
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.copy_layout_pin(self.delay_inst,"gnd")
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self.copy_layout_pin(self.delay_inst,"vdd")
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self.copy_layout_pin(self.delay_inst,"gnd")
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self.copy_layout_pin(self.delay_inst,"vdd")
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self.copy_layout_pin(self.ctrl_dff_inst,"gnd")
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self.copy_layout_pin(self.ctrl_dff_inst,"vdd")
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@ -958,3 +971,11 @@ class control_logic(design.design):
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self.graph_inst_exclude.add(self.ctrl_dff_inst)
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if self.port_type=="rw" or self.port_type=="w":
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self.graph_inst_exclude.add(self.w_en_gate_inst)
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def place_util(self, inst, x_offset, row):
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""" Utility to place a row and compute the next offset """
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(y_offset,mirror)=self.get_offset(row)
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offset = vector(x_offset, y_offset)
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inst.place(offset, mirror)
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return x_offset+inst.width
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