mirror of https://github.com/VLSIDA/OpenRAM.git
Two m1 pitches at top of control logic
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@ -195,7 +195,7 @@ class control_logic(design.design):
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self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y)
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self.control_logic_center = vector(self.ctrl_dff_inst.rx(), control_center_y)
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# Extra pitch on top and right
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# Extra pitch on top and right
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self.height = height + self.m2_pitch
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self.height = height + 2*self.m1_pitch
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# Max of modules or logic rows
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# Max of modules or logic rows
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if (self.port_type == "rw") or (self.port_type == "r"):
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if (self.port_type == "rw") or (self.port_type == "r"):
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self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch
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self.width = max(self.rbl_inst.rx(), max([inst.rx() for inst in self.row_end_inst])) + self.m2_pitch
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