Merge branch 'dev' into char

compiler/modules/__init__.py

@@ -80,3 +80,4 @@ from .write_mask_and_array import *
 from .sram_1bank import *
 from .sram_config import *
 from .sram import *
+from .internal_base import *

compiler/modules/bitcell_1port.py

@@ -29,7 +29,3 @@ class bitcell_1port(bitcell_base):
         """
         self.add_graph_edges(graph, port_nets)
 
-    def is_non_inverting(self):
-        """Return input to output polarity for module"""
-
-        return False

compiler/modules/bitcell_2port.py

@@ -99,8 +99,3 @@ class bitcell_2port(bitcell_base):
         # Port 1 edges
         graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
         graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
-
-    def is_non_inverting(self):
-        """Return input to output polarity for module"""
-
-        return False

compiler/modules/bitcell_base.py

@@ -265,3 +265,15 @@ class bitcell_base(design):
             delay = math.sqrt(2*tstep*(vdd-spice["nom_threshold"])/m)
 
         return delay
+
+    def build_graph(self, graph, inst_name, port_nets):
+        """
+        Adds edges based on inputs/outputs.
+        Overrides base class function.
+        """
+        debug.error("Must override build_graph function in bitcell base class.")
+
+    def is_non_inverting(self):
+        """Return input to output polarity for module"""
+
+        return False

compiler/modules/internal_base.py

@@ -0,0 +1,14 @@
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+
+from base import design
+
+class internal_base(design):
+
+    def __init__(self, name, cell_name=None, prop=None):
+        design.__init__(self, name, cell_name, prop)