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Add dummy bitcell module.

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Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
This commit is contained in:
mrg
2019-07-05 12:58:52 -07:00
parent f542613d78
commit b9d993c88b
12 changed files with 208 additions and 76 deletions
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compiler/tests/05_bitcell_1rw_1r_array_test.py
-1
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@@ -23,7 +23,6 @@ class bitcell_1rw_1r_array_test(openram_test):
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
compiler/tests/05_replica_bitcell_array_test.py
+10 -1
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@@ -19,9 +19,18 @@ class replica_bitcell_array_test(openram_test):
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing 4x4 array for 6t_cell")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4)
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, num_ports=1)
self.local_check(a)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
factory.reset()
debug.info(2, "Testing 4x4 array for 6t_cell")
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, num_ports=2)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/05_replica_column_test.py
+5 -1
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@@ -19,9 +19,13 @@ class replica_column_test(openram_test):
globals.init_openram("config_{0}".format(OPTS.tech_name))
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column", rows=4)
a = factory.create(module_type="replica_column", rows=4, num_ports=1)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column", rows=4, num_ports=2)
self.local_check(a)
globals.end_openram()
# run the test from the command line
compiler/tests/14_replica_bitline_multiport_test.py
+2
View File
@@ -26,6 +26,7 @@ class replica_bitline_multiport_test(openram_test):
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r"
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
@@ -38,6 +39,7 @@ class replica_bitline_multiport_test(openram_test):
# check replica bitline in pbitcell multi-port
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0