mirror of https://github.com/VLSIDA/OpenRAM.git
Fix for Missing lef_rom_interconnect in tech.py
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@ -67,6 +67,9 @@ m1_stack = ("m1", "via1", "m2")
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m2_stack = ("m2", "via2", "m3")
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m3_stack = ("m3", "via3", "m4")
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# Added to support ROM generation
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lef_rom_interconnect = ["m1", "m2", "m3", "m4", "m5"]
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layer_indices = {"poly": 0,
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"active": 0,
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"m1": 1,
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