mirror of https://github.com/VLSIDA/OpenRAM.git
TODO for make characterizer a module
This commit is contained in:
parent
16ea09293c
commit
b9ad65c1de
|
|
@ -34,4 +34,6 @@ remove the dependency on the clock period.
|
||||||
Remove duplicate clock inverter in MS flop.
|
Remove duplicate clock inverter in MS flop.
|
||||||
|
|
||||||
Make lib file have delay relative to negedge for DATA. Must update
|
Make lib file have delay relative to negedge for DATA. Must update
|
||||||
timing code too.
|
timing code too.
|
||||||
|
|
||||||
|
Convert characterizer into a Python package
|
||||||
Loading…
Reference in New Issue