mirror of https://github.com/VLSIDA/OpenRAM.git
TODO for make characterizer a module
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@ -35,3 +35,5 @@ Remove duplicate clock inverter in MS flop.
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Make lib file have delay relative to negedge for DATA. Must update
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Make lib file have delay relative to negedge for DATA. Must update
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timing code too.
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timing code too.
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Convert characterizer into a Python package
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