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Add labels to noconn in dummy bitcell for klayout lvs

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mrg 2021-11-22 10:37:26 -08:00
parent 735f9cf450
commit b94dd79125
1 changed files with 44 additions and 0 deletions
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44
compiler/bitcells/pbitcell.py
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@ -474,6 +474,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.connect_inst([self.Q_bar, self.connect_inst([self.Q_bar,
self.rw_wl_names[k], br_name, "gnd"]) self.rw_wl_names[k], br_name, "gnd"])
def place_readwrite_ports(self): def place_readwrite_ports(self):
""" Places read/write ports in the bit cell """ """ Places read/write ports in the bit cell """
# define read/write transistor variables as empty arrays # define read/write transistor variables as empty arrays
@ -528,6 +529,21 @@ class pbitcell(bitcell_base.bitcell_base):
offset=self.rwbr_positions[k], offset=self.rwbr_positions[k],
height=self.height) height=self.height)
if self.dummy_bitcell:
bl_name = self.rw_bl_names[k]
br_name = self.rw_br_names[k]
bl_name += "_noconn"
br_name += "_noconn"
# This helps with LVS matching in klayout
drain_pin = self.readwrite_nmos_left[k].get_pin("S")
self.add_label(bl_name, drain_pin.layer, drain_pin.center())
# This helps with LVS matching in klayout
source_pin = self.readwrite_nmos_right[k].get_pin("D")
self.add_label(br_name, source_pin.layer, source_pin.center())
# update furthest left and right transistor edges # update furthest left and right transistor edges
self.left_building_edge = left_readwrite_transistor_xpos self.left_building_edge = left_readwrite_transistor_xpos
self.right_building_edge = right_readwrite_transistor_xpos \ self.right_building_edge = right_readwrite_transistor_xpos \
@ -625,6 +641,20 @@ class pbitcell(bitcell_base.bitcell_base):
offset=self.wbr_positions[k], offset=self.wbr_positions[k],
height=self.height) height=self.height)
if self.dummy_bitcell:
bl_name = self.w_bl_names[k]
br_name = self.w_br_names[k]
bl_name += "_noconn"
br_name += "_noconn"
# This helps with LVS matching in klayout
drain_pin = self.write_nmos_left[k].get_pin("S")
self.add_label(bl_name, drain_pin.layer, drain_pin.center())
# This helps with LVS matching in klayout
source_pin = self.write_nmos_right[k].get_pin("D")
self.add_label(br_name, source_pin.layer, source_pin.center())
# update furthest left and right transistor edges # update furthest left and right transistor edges
self.left_building_edge = left_write_transistor_xpos self.left_building_edge = left_write_transistor_xpos
self.right_building_edge = right_write_transistor_xpos \ self.right_building_edge = right_write_transistor_xpos \
@ -752,6 +782,20 @@ class pbitcell(bitcell_base.bitcell_base):
offset=self.rbr_positions[k], offset=self.rbr_positions[k],
height=self.height) height=self.height)
if self.dummy_bitcell:
bl_name = self.r_bl_names[k]
br_name = self.r_br_names[k]
bl_name += "_noconn"
br_name += "_noconn"
# This helps with LVS matching in klayout
drain_pin = self.read_access_nmos_left[k].get_pin("S")
self.add_label(bl_name, drain_pin.layer, drain_pin.center())
# This helps with LVS matching in klayout
source_pin = self.read_access_nmos_right[k].get_pin("D")
self.add_label(br_name, source_pin.layer, source_pin.center())
def route_wordlines(self): def route_wordlines(self):
""" Routes gate of transistors to their respective wordlines """ """ Routes gate of transistors to their respective wordlines """
port_transistors = [] port_transistors = []