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Fix functional script spice file name and unit test
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@@ -8,6 +8,8 @@
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import math
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import random
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import collections
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from os import path
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import shutil
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from numpy import binary_repr
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from openram import debug
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from openram import OPTS
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@@ -33,6 +35,9 @@ class functional(simulation):
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if not spfile:
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# self.sp_file is assigned in base class
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sram.sp_write(self.sp_file, trim=OPTS.trim_netlist)
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# Copy sp file to temp dir
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self.temp_spice = path.join(OPTS.openram_temp, "sram.sp")
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shutil.copy(self.sp_file, self.temp_spice)
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if not corner:
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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@@ -386,16 +391,16 @@ class functional(simulation):
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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self.stim_sp = "functional_stim.sp"
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temp_stim = "{0}/{1}".format(self.output_path, self.stim_sp)
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temp_stim = path.join(self.output_path, self.stim_sp)
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self.sf = open(temp_stim, "w")
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self.sf.write("* Functional test stimulus file for {0}ns period\n\n".format(self.period))
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self.meas_sp = "functional_meas.sp"
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temp_meas = "{0}/{1}".format(self.output_path, self.meas_sp)
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temp_meas = path.join(self.output_path, self.meas_sp)
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self.mf = open(temp_meas, "w")
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self.stim = stimuli(self.sf, self.mf, self.corner)
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# Write include statements
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self.stim.write_include(self.sp_file)
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self.stim.write_include(self.temp_spice)
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# Write Vdd/Gnd statements
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self.sf.write("\n* Global Power Supplies\n")
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@@ -502,9 +507,11 @@ class functional(simulation):
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# dout=signal_name,
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# t_initial=t_initial,
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# t_final=t_final)
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self.sf.write(".include {0}\n".format(temp_meas))
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self.stim.write_control(self.cycle_times[-1] + self.period)
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self.sf.close()
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self.mf.close()
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# FIXME: Similar function to delay.py, refactor this
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def get_bit_name(self):
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