Replica bitcell array with arbitrary RBLs working

2026-08-29 17:39:02 +02:00 · 2019-07-10 15:56:51 -07:00
parent 9dab0be737
commit b841fd7ce3
19 changed files with 565 additions and 596 deletions
@@ -60,6 +60,8 @@ class openram_test(unittest.TestCase):
                #shutil.make_archive(zip_file, 'zip', OPTS.openram_temp)
                self.fail("LVS mismatch: {}".format(a.name))

+        # For debug...
+        #import pdb; pdb.set_trace()
        if OPTS.purge_temp:
            self.cleanup()