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Replica bitcell array with arbitrary RBLs working
This commit is contained in:
mrg
@@ -22,18 +22,25 @@ class replica_bitcell_array(design.design):
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Dummy are the outside columns/rows with WL and BL tied to gnd.
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Requires a regular bitcell array, replica bitcell, and dummy bitcell (Bl/BR disconnected).
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"""
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def __init__(self, cols, rows, num_ports, name):
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def __init__(self, cols, rows, left_rbl, right_rbl, name):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, rows, cols))
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self.add_comment("rows: {0} cols: {1}".format(rows, cols))
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self.column_size = cols
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self.row_size = rows
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self.num_ports = num_ports
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self.left_rbl = left_rbl
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self.right_rbl = right_rbl
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# FIXME: If we want more than 2 ports of RBL, we also need to modify
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# replica_column to support this. Right now, it only supports a single
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# RBL and is used for both the left and right column (right is flipped).
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#debug.check(self.left_rbl<=1,"Only one RBL supported now.")
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#debug.check(self.right_rbl<=1,"Only one RBL supported now.")
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# Two dummy rows/cols plus replica for each port
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self.extra_rows = 2 + self.num_ports
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self.extra_cols = 2 + self.num_ports
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self.extra_rows = 2 + left_rbl + right_rbl
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self.extra_cols = 2 + left_rbl + right_rbl
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self.create_netlist()
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if not OPTS.netlist_only:
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@@ -83,22 +90,32 @@ class replica_bitcell_array(design.design):
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rows=self.row_size)
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self.add_mod(self.bitcell_array)
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# Replica bitline
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self.replica_column = factory.create(module_type="replica_column",
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rows=self.row_size + self.extra_rows,
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num_ports = self.num_ports)
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self.add_mod(self.replica_column)
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# Replica bitlines
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self.replica_columns = {}
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for bit in range(self.left_rbl+self.right_rbl):
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if bit<self.left_rbl:
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replica_bit = bit+1
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else:
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replica_bit = bit+self.row_size+1
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self.replica_columns[bit] = factory.create(module_type="replica_column",
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rows=self.row_size,
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left_rbl=self.left_rbl,
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right_rbl=self.right_rbl,
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[bit])
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# Dummy row
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self.dummy_row = factory.create(module_type="dummy_array",
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cols=self.column_size,
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rows=1)
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rows=1,
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mirror=0)
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self.add_mod(self.dummy_row)
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# Dummy col
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# Dummy col (mirror starting at first if odd replica+dummy rows)
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self.dummy_col = factory.create(module_type="dummy_array",
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cols=1,
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rows=self.row_size + self.extra_rows)
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rows=self.row_size + self.extra_rows,
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mirror=(self.left_rbl+1)%2)
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self.add_mod(self.dummy_col)
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@@ -108,115 +125,146 @@ class replica_bitcell_array(design.design):
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self.wl_names = [x for x in self.bitcell_array.pins if x.startswith("w")]
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self.bl_names = [x for x in self.bitcell_array.pins if x.startswith("b")]
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# top/bottom rows (in the middle)
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self.replica_wl_names = ["replica_"+x for x in self.cell.list_all_wl_names()]
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self.dummy_wl_names = ["dummy_"+x for x in self.cell.list_all_wl_names()]
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self.dummy_bl_names = ["dummy_"+x for x in self.cell.list_all_bitline_names()]
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# These are the non-indexed names
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self.replica_cell_wl_names = ["replica_"+x for x in self.cell.list_all_wl_names()]
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self.dummy_cell_wl_names = ["dummy_"+x for x in self.cell.list_all_wl_names()]
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self.dummy_cell_bl_names = ["dummy_"+x for x in self.cell.list_all_bitline_names()]
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self.dummy_row_bl_names = self.bl_names
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# dummy row and replica on each side of the bitcell rows
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self.replica_col_wl_names = [x+"_0" for x in self.dummy_wl_names] \
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+ ["replica_"+x+"_0" for x in self.cell.list_all_wl_names()] \
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+ self.wl_names
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if self.num_ports==2:
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self.replica_col_wl_names.extend(["replica_"+x+"_1" for x in self.cell.list_all_wl_names()])
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self.replica_col_wl_names.extend([x+"_1" for x in self.dummy_wl_names])
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self.replica_bl_names = ["replica_"+x for x in self.cell.list_all_bitline_names()]
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self.replica_bl0_names = [x+"_0" for x in self.replica_bl_names]
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self.replica_bl1_names = [x+"_1" for x in self.replica_bl_names]
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# left/right rows
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# Create the full WL names include dummy, replica, and regular bit cells
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self.replica_col_wl_names = []
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self.replica_col_wl_names.extend(["{0}_bot".format(x) for x in self.dummy_cell_wl_names])
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# Left port WLs (one dummy for each port when we allow >1 port)
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for bit in range(self.left_rbl):
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self.replica_col_wl_names.extend(["replica_{0}_{1}".format(x,bit) for x in self.cell.list_all_wl_names()])
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# Regular WLs
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self.replica_col_wl_names.extend(self.wl_names)
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# Right port WLs (one dummy for each port when we allow >1 port)
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for bit in range(self.left_rbl,self.left_rbl+self.right_rbl):
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self.replica_col_wl_names.extend(["replica_{0}_{1}".format(x,bit) for x in self.cell.list_all_wl_names()])
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self.replica_col_wl_names.extend(["{0}_top".format(x) for x in self.dummy_cell_wl_names])
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# Left/right dummy columns are connected identically to the replica column
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self.dummy_col_wl_names = self.replica_col_wl_names
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# Per bit bitline names
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self.replica_bl_names_list = {}
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self.replica_wl_names_list = {}
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# Array of all bitline names
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self.replica_bl_names = []
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self.replica_wl_names = []
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for bit in range(self.left_rbl+self.right_rbl):
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self.replica_bl_names_list[bit] = ["replica_{0}_{1}".format(x,bit) for x in self.cell.list_all_bitline_names()]
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self.replica_bl_names.extend(self.replica_bl_names_list[bit])
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self.replica_wl_names_list[bit] = ["{0}_{1}".format(x,bit) for x in self.replica_cell_wl_names]
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self.replica_wl_names.extend(self.replica_wl_names_list[bit])
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self.add_pin_list(self.bl_names)
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self.add_pin_list(self.replica_bl0_names)
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if self.num_ports==2:
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self.add_pin_list(self.replica_bl1_names)
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self.add_pin_list(self.replica_bl_names)
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self.add_pin_list(self.wl_names)
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self.add_pin_list(self.replica_wl_names)
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#self.add_pin_list([x for x in self.replica_col_wl_names if not x.startswith("dummy")])
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self.add_pin("vdd")
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self.add_pin("gnd")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def create_instances(self):
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""" Create the module instances used in this design """
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supplies = ["vdd", "gnd"]
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# Used for names/dimensions only
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self.cell = factory.create(module_type="bitcell")
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# Main array
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self.bitcell_array_inst=self.add_inst(name="bitcell_array",
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mod=self.bitcell_array)
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self.connect_inst(self.bitcell_array.pins)
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# Replica columns (two even if one port for now)
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self.replica_col_left_inst=self.add_inst(name="replica_col_left",
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mod=self.replica_column)
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self.connect_inst(self.replica_bl0_names + self.replica_col_wl_names + supplies)
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# Replica columns
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self.replica_col_inst = {}
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for bit in range(self.left_rbl):
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self.replica_col_inst[bit]=self.add_inst(name="replica_col_left_{}".format(bit),
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mod=self.replica_columns[bit])
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self.connect_inst(self.replica_bl_names_list[bit] + self.replica_col_wl_names + supplies)
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if self.num_ports==2:
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self.replica_col_right_inst=self.add_inst(name="replica_col_right",
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mod=self.replica_column)
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self.connect_inst(self.replica_bl1_names + self.replica_col_wl_names[::-1] + supplies)
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for bit in range(self.left_rbl,self.left_rbl+self.right_rbl):
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self.replica_col_inst[bit]=self.add_inst(name="replica_col_right_{}".format(bit),
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mod=self.replica_columns[bit])
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self.connect_inst(self.replica_bl_names_list[bit] + self.replica_col_wl_names + supplies)
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# Replica rows with replica bitcell
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self.dummy_row_bottop_inst=self.add_inst(name="dummy_row_bottop",
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + [x+"_0" for x in self.replica_wl_names] + supplies)
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self.dummy_row_topbot_inst=self.add_inst(name="dummy_row_topbot",
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + [x+"_1" for x in self.replica_wl_names] + supplies)
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self.dummy_row_replica_inst = {}
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for bit in range(self.left_rbl+self.right_rbl):
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self.dummy_row_replica_inst[bit]=self.add_inst(name="dummy_row_{}".format(bit),
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + self.replica_wl_names_list[bit] + supplies)
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# Dummy rows without replica bitcell
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self.dummy_row_botbot_inst=self.add_inst(name="dummy_row_botbot",
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# Top/bottom dummy rows
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self.dummy_row_bot_inst=self.add_inst(name="dummy_row_bot",
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + [x+"_0" for x in self.dummy_wl_names] + supplies)
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self.dummy_row_toptop_inst=self.add_inst(name="dummy_row_toptop",
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self.connect_inst(self.dummy_row_bl_names + [x+"_bot" for x in self.dummy_cell_wl_names] + supplies)
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self.dummy_row_top_inst=self.add_inst(name="dummy_row_top",
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mod=self.dummy_row)
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self.connect_inst(self.dummy_row_bl_names + [x+"_1" for x in self.dummy_wl_names] + supplies)
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self.connect_inst(self.dummy_row_bl_names + [x+"_top" for x in self.dummy_cell_wl_names] + supplies)
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# Dummy columns
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# Left/right Dummy columns
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self.dummy_col_left_inst=self.add_inst(name="dummy_col_left",
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mod=self.dummy_col)
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self.connect_inst([x+"_0" for x in self.dummy_bl_names] + self.dummy_col_wl_names + supplies)
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self.connect_inst([x+"_left" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies)
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self.dummy_col_right_inst=self.add_inst(name="dummy_col_right",
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mod=self.dummy_col)
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self.connect_inst([x+"_1" for x in self.dummy_bl_names] + self.dummy_col_wl_names + supplies)
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self.connect_inst([x+"_right" for x in self.dummy_cell_bl_names] + self.dummy_col_wl_names + supplies)
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def create_layout(self):
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self.height = (self.row_size+self.extra_rows)*self.dummy_row.height
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self.width = (self.column_size+self.extra_cols)*self.replica_column.width
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self.width = (self.column_size+self.extra_cols)*self.cell.width
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# This is a bitcell x bitcell offset to scale
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offset = vector(self.replica_column.width, self.dummy_row.height)
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offset = vector(self.cell.width, self.cell.height)
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self.bitcell_array_inst.place(offset=[0,0])
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self.replica_col_left_inst.place(offset=offset.scale(-1,-2))
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if self.num_ports==2:
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self.replica_col_right_inst.place(offset=offset.scale(0,2)+self.bitcell_array_inst.ur(),
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mirror="MX")
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self.dummy_row_toptop_inst.place(offset=offset.scale(0,2)+self.bitcell_array_inst.ul(),
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mirror="MX")
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self.dummy_row_topbot_inst.place(offset=offset.scale(0,0)+self.bitcell_array_inst.ul())
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self.dummy_row_bottop_inst.place(offset=offset.scale(0,0),
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mirror="MX")
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self.dummy_row_botbot_inst.place(offset=offset.scale(0,-2))
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self.dummy_col_left_inst.place(offset=offset.scale(-2,-2))
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if self.num_ports==2:
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self.dummy_col_right_inst.place(offset=offset.scale(1,-2)+self.bitcell_array_inst.lr())
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else:
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self.dummy_col_right_inst.place(offset=offset.scale(0,-2)+self.bitcell_array_inst.lr())
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# To the left of the bitcell array
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for bit in range(self.left_rbl):
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self.replica_col_inst[bit].place(offset=offset.scale(-bit-1,-self.left_rbl-1))
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# To the right of the bitcell array
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for bit in range(self.right_rbl):
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self.replica_col_inst[self.left_rbl+bit].place(offset=offset.scale(bit,-self.left_rbl-1)+self.bitcell_array_inst.lr())
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# Far top dummy row (first row above array is NOT flipped)
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flip_dummy = self.right_rbl%2
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self.dummy_row_top_inst.place(offset=offset.scale(0,self.right_rbl+flip_dummy)+self.bitcell_array_inst.ul(),
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mirror="MX" if flip_dummy else "R0")
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# Far bottom dummy row (first row below array IS flipped)
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flip_dummy = (self.left_rbl+1)%2
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self.dummy_row_bot_inst.place(offset=offset.scale(0,-self.left_rbl-1+flip_dummy),
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mirror="MX" if flip_dummy else "R0")
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# Far left dummy col
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self.dummy_col_left_inst.place(offset=offset.scale(-self.left_rbl-1,-self.left_rbl-1))
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# Far right dummy col
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self.dummy_col_right_inst.place(offset=offset.scale(self.right_rbl,-self.left_rbl-1)+self.bitcell_array_inst.lr())
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# Replica dummy rows
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for bit in range(self.left_rbl):
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self.dummy_row_replica_inst[bit].place(offset=offset.scale(0,-bit-bit%2),
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mirror="R0" if bit%2 else "MX")
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for bit in range(self.right_rbl):
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self.dummy_row_replica_inst[self.left_rbl+bit].place(offset=offset.scale(0,bit+bit%2)+self.bitcell_array_inst.ul(),
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mirror="MX" if bit%2 else "R0")
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self.translate_all(offset.scale(-2,-2))
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self.translate_all(offset.scale(-1-self.left_rbl,-1-self.left_rbl))
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self.add_layout_pins()
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@@ -234,52 +282,50 @@ class replica_bitcell_array(design.design):
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if pin_name.startswith("wl"):
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=self.width,
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height=pin.height())
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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elif pin_name.startswith("bl") or pin_name.startswith("br"):
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pin_list = self.bitcell_array_inst.get_pins(pin_name)
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for pin in pin_list:
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self.add_layout_pin_rect_center(text=pin_name,
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layer=pin.layer,
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offset=pin.center(),
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width=pin.width(),
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height=self.height)
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self.add_layout_pin(text=pin_name,
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layer=pin.layer,
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offset=pin.ll().scale(1,0),
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width=pin.width(),
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height=self.height)
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for index,(side1,side2) in enumerate([("bottop","left"),("topbot","right")]):
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inst = getattr(self, "dummy_row_{}_inst".format(side1))
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pin_names = inst.mod.get_pin_names()
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for pin_name in pin_names:
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if pin_name.startswith("wl"):
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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name = "replica_{0}_{1}".format(pin_name,index)
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self.add_layout_pin_rect_center(text=name,
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layer=pin.layer,
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offset=pin.center(),
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width=self.width,
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height=pin.height())
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# Replica wordlines
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for bit in range(self.left_rbl+self.right_rbl):
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inst = self.replica_col_inst[bit]
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for (pin_name,wl_name) in zip(self.cell.list_all_wl_names(),self.replica_wl_names_list[bit]):
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# +1 for dummy row
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pin_bit = bit+1
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# +row_size if above the array
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if bit>=self.left_rbl:
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pin_bit += self.row_size
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pin_name += "_{}".format(pin_bit)
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pin = inst.get_pin(pin_name)
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self.add_layout_pin(text=wl_name,
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layer=pin.layer,
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offset=pin.ll().scale(0,1),
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width=self.width,
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height=pin.height())
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# Replica columns
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replica_sides = ["left"]
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if self.num_ports==2:
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replica_sides.append("right")
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for index,side in enumerate(replica_sides):
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inst = getattr(self, "replica_col_{}_inst".format(side))
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pin_names = inst.mod.get_pin_names()
|
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for pin_name in pin_names:
|
||||
if pin_name.startswith("bl") or pin_name.startswith("br"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
name = "replica_{0}_{1}".format(pin_name,index)
|
||||
self.add_layout_pin(text=name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1,0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
# Replica bitlines
|
||||
for bit in range(self.left_rbl+self.right_rbl):
|
||||
inst = self.replica_col_inst[bit]
|
||||
for (pin_name, bl_name) in zip(self.cell.list_all_bitline_names(),self.replica_bl_names_list[bit]):
|
||||
pin = inst.get_pin(pin_name)
|
||||
name = "replica_{0}_{1}".format(pin_name,bit)
|
||||
self.add_layout_pin(text=name,
|
||||
layer=pin.layer,
|
||||
offset=pin.ll().scale(1,0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
|
||||
for pin_name in ["vdd","gnd"]:
|
||||
@@ -291,17 +337,17 @@ class replica_bitcell_array(design.design):
|
||||
|
||||
# Non-pins
|
||||
|
||||
for side in ["botbot", "toptop"]:
|
||||
for side in ["bot", "top"]:
|
||||
inst = getattr(self, "dummy_row_{}_inst".format(side))
|
||||
pin_names = inst.mod.get_pin_names()
|
||||
for pin_name in pin_names:
|
||||
if pin_name.startswith("wl"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_rect_center(layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
self.add_rect(layer=pin.layer,
|
||||
offset=pin.ll().scale(0,1),
|
||||
width=self.width,
|
||||
height=pin.height())
|
||||
|
||||
|
||||
for side in ["left", "right"]:
|
||||
@@ -311,10 +357,10 @@ class replica_bitcell_array(design.design):
|
||||
if pin_name.startswith("b"):
|
||||
pin_list = inst.get_pins(pin_name)
|
||||
for pin in pin_list:
|
||||
self.add_rect_center(layer=pin.layer,
|
||||
offset=pin.center(),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
self.add_rect(layer=pin.layer,
|
||||
offset=pin.ll().scale(1,0),
|
||||
width=pin.width(),
|
||||
height=self.height)
|
||||
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user