Added initial code for determining the logical effort delay of the wordline.

compiler/pgates/pinv.py

@@ -7,6 +7,7 @@ from vector import vector
 from math import ceil
 from globals import OPTS
 from utils import round_to_grid
+import logical_effort
 
 class pinv(pgate.pgate):
     """
@@ -29,7 +30,8 @@ class pinv(pgate.pgate):
         pinv.unique_id += 1
         pgate.pgate.__init__(self, name, height)
         debug.info(2, "create pinv structure {0} with size of {1}".format(name, size))
-
+        
+        self.size = size
         self.nmos_size = size
         self.pmos_size = beta*size
         self.beta = beta
@@ -281,3 +283,12 @@ class pinv(pgate.pgate):
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
         transition_prob = spice["inv_transition_prob"]
         return transition_prob*(c_load + c_para) 
+
+    def get_cin(self):
+        """Return the capacitance of the gate connection in generic capacitive units relative to the minimum width of a transistor"""
+        return self.nmos_size + self.pmos_size
+        
+    def get_effort_stage(self, cout):
+        """Returns an object representing the parameters for delay in tau units."""
+        parasitic_delay = 1 
+        return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay)

compiler/pgates/pinvbuf.py

@@ -187,3 +187,14 @@ class pinvbuf(design.design):
         inv2_delay = self.inv2.analytical_delay(slew=inv1_delay.slew, load=load)
         return inv1_delay + inv2_delay
             
+    def determine_wordline_stage_efforts(self, external_cout):
+        """Get the stage efforts of the clk -> clk_buf path"""
+        stage_effort_list = []
+        stage1_cout = self.inv1.get_cin() + self.inv2.get_cin()
+        stage1 = self.inv.get_effort_stage(stage1_cout)
+        stage_effort_list.append(stage1)
+        
+        stage2 = self.inv2.get_effort_stage(external_cout)
+        stage_effort_list.append(stage2)
+        
+        return stage_effort_list

compiler/pgates/pnand2.py

@@ -5,6 +5,7 @@ from tech import drc, parameter, spice
 from ptx import ptx
 from vector import vector
 from globals import OPTS
+import logical_effort
 
 class pnand2(pgate.pgate):
     """
@@ -21,6 +22,7 @@ class pnand2(pgate.pgate):
         pgate.pgate.__init__(self, name, height)
         debug.info(2, "create pnand2 structure {0} with size of {1}".format(name, size))
 
+        self.size = size
         self.nmos_size = 2*size
         self.pmos_size = parameter["beta"]*size
         self.nmos_width = self.nmos_size*drc("minwidth_tx")
@@ -242,3 +244,12 @@ class pnand2(pgate.pgate):
         c_para = spice["min_tx_drain_c"]*(self.nmos_size/parameter["min_tx_size"])#ff
         transition_prob = spice["nand2_transition_prob"]
         return transition_prob*(c_load + c_para) 
+
+    def get_cin(self):
+        """Return the relative input capacitance of a single input"""
+        return self.nmos_size+self.pmos_size
+        
+    def get_effort_stage(self, cout):
+        """Returns an object representing the parameters for delay in tau units."""
+        parasitic_delay = 2 
+        return logical_effort.logical_effort(self.size, self.get_cin(), cout, parasitic_delay)