Added initial code for determining the logical effort delay of the wordline.

compiler/modules/bank.py

@@ -950,4 +950,18 @@ class bank(design.design):
             results.append(decoder_delay + word_driver_delay + bitcell_array_delay + column_mux_delay + bl_t_data_out_delay) 
 
         return results
+         
+    def determine_wordline_stage_efforts(self, external_cout):    
+        """Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline"""
+        #Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption
+        stage_effort_list = []
+        wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout
+        stage_effort_list += self.wordline_driver.determine_wordline_stage_efforts(wordline_cout)
         
+        return stage_effort_list
+        
+    def get_clk_cin(self):
+        """Get the relative capacitance of all the clk connections in the bank"""
+        #Current bank only uses clock (clk_buf) as an enable for the wordline driver.
+        total_clk_cin = self.wordline_driver.get_clk_cin()
+        return total_clk_cin

compiler/modules/bitcell_array.py

@@ -225,3 +225,10 @@ class bitcell_array(design.design):
     def input_load(self):
         wl_wire = self.gen_wl_wire()
         return wl_wire.return_input_cap()
+
+    def get_wordline_cin(self):
+        """Get the relative input capacitance from the wordline connections in all the bitcell"""
+        #A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
+        bitcell_wl_cin = self.cell.get_wl_cin()
+        total_cin = bitcell_wl_cin * self.column_size
+        return total_cin

compiler/modules/control_logic.py

@@ -596,4 +596,14 @@ class control_logic(design.design):
                            height=pin.height(),
                            width=pin.width())
         
+    def determine_wordline_stage_efforts(self, external_cout):
+        """Follows the clock signal to the clk_buf signal adding each stages stage effort to a list"""
+        stage_effort_list = []
+        #Calculate the load on clk_buf within the module and add it to external load
+        internal_cout = self.ctrl_dff_array.get_clk_cin()
+        clk_buf_cap = internal_cout+external_cout
+        #First stage is the clock buffer
+        stage_effort_list += self.clkbuf.determine_wordline_stage_efforts(clk_buf_cap)
         
+        return stage_effort_list
+        

compiler/modules/dff.py

@@ -2,7 +2,7 @@ import globals
 import design
 from math import log
 import design
-from tech import GDS,layer
+from tech import GDS,layer,spice,parameter
 import utils
 
 class dff(design.design):
@@ -23,7 +23,6 @@ class dff(design.design):
     
     def analytical_power(self, proc, vdd, temp, load):
         """Returns dynamic and leakage power. Results in nW"""
-        from tech import spice
         c_eff = self.calculate_effective_capacitance(load)
         f = spice["default_event_rate"]
         power_dyn = c_eff*vdd*vdd*f
@@ -34,7 +33,7 @@ class dff(design.design):
         
     def calculate_effective_capacitance(self, load):
         """Computes effective capacitance. Results in fF"""
-        from tech import spice, parameter
+        from tech import parameter
         c_load = load
         c_para = spice["flop_para_cap"]#ff
         transition_prob = spice["flop_transition_prob"]
@@ -42,7 +41,12 @@ class dff(design.design):
 
     def analytical_delay(self, slew, load = 0.0):
         # dont know how to calculate this now, use constant in tech file
-        from tech import spice
         result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
         return result
+        
+    def get_clk_cin(self):
+        """Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
+        #This is a handmade cell so the value must be entered in the tech.py file or estimated.
+        #Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
+        return parameter["dff_clk_cin"]
 

compiler/modules/dff_array.py

@@ -157,3 +157,9 @@ class dff_array(design.design):
 
     def analytical_delay(self, slew, load=0.0):
         return self.dff.analytical_delay(slew=slew, load=load)
+
+    def get_clk_cin(self):
+        """Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
+        dff_clk_cin = self.dff.get_clk_cin()
+        total_cin = dff_clk_cin * self.rows * self.columns
+        return total_cin

compiler/modules/dff_inv.py

@@ -148,3 +148,6 @@ class dff_inv(design.design):
         inv1_delay = self.inv1.analytical_delay(slew=dff_delay.slew, load=load) 
         return dff_delay + inv1_delay 
             
+    def get_clk_cin(self):
+        """Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
+        return self.dff.get_clk_cin()

compiler/modules/dff_inv_array.py

@@ -182,3 +182,9 @@ class dff_inv_array(design.design):
 
     def analytical_delay(self, slew, load=0.0):
         return self.dff.analytical_delay(slew=slew, load=load)
+
+    def get_clk_cin(self):
+        """Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
+        dff_clk_cin = self.dff.get_clk_cin()
+        total_cin = dff_clk_cin * self.rows * self.columns
+        return total_cin

compiler/modules/wordline_driver.py

@@ -238,4 +238,27 @@ class wordline_driver(design.design):
 
         
     def input_load(self):
+        """Gets the capacitance of the wordline driver in absolute units (fF)"""
         return self.nand2.input_load()
+
+    def determine_wordline_stage_efforts(self, external_cout):
+        """Follows the clk_buf to a wordline signal adding each stages stage effort to a list"""
+        stage_effort_list = []
+        stage1_cout = self.nand2.get_cin()
+        stage1 = self.inv_no_output.get_effort_stage(stage1_cout)
+        stage_effort_list.append(stage1)
+        
+        stage2_cout = self.inv.get_cin()
+        stage2 = self.nand2.get_effort_stage(stage2_cout)
+        stage_effort_list.append(stage2)
+        
+        stage3 = self.inv.get_effort_stage(external_cout)
+        stage_effort_list.append(stage3)
+        
+        return stage_effort_list
+        
+    def get_clk_cin(self):
+        """Get the relative capacitance of all the clk connections in the bank"""
+        #Clock is connected as an input to 1 inverter per row
+        total_cin = self.inv_no_output.get_cin() * self.rows
+        return total_cin