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https://github.com/VLSIDA/OpenRAM.git
synced 2026-08-30 01:48:33 +02:00
Changes to simplify metal preferred directions and pitches.
Changes to allow decoder height to be a 2x multiple of bitcell height. Split of control logic tests. Fixed track spacing in SRAM and channel router PEP8 cleanup.
This commit is contained in:
mrg
@@ -5,9 +5,7 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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@@ -43,33 +41,28 @@ class write_mask_and_array(design.design):
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self.add_pins()
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self.create_and2_array()
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def create_layout(self):
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self.place_and2_array()
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spacing = self.wmask_en_len - self.and2.width
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self.width = (self.num_wmasks*self.and2.width) + ((self.num_wmasks-1)*spacing)
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self.height = self.and2.height
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self.add_layout_pins()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for bit in range(self.num_wmasks):
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self.add_pin("wmask_in_{}".format(bit),"INPUT")
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self.add_pin("wmask_in_{}".format(bit), "INPUT")
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self.add_pin("en", "INPUT")
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for bit in range(self.num_wmasks):
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self.add_pin("wmask_out_{}".format(bit),"OUTPUT")
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self.add_pin("vdd","POWER")
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self.add_pin("gnd","GROUND")
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self.add_pin("wmask_out_{}".format(bit), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
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# Assume stage effort of 3 to compute the size
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self.and2 = factory.create(module_type="pand2",
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size=self.write_size/4.0)
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size=self.write_size / 4.0)
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self.add_mod(self.and2)
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def create_and2_array(self):
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self.and2_insts = {}
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for bit in range(self.num_wmasks):
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@@ -81,7 +74,6 @@ class write_mask_and_array(design.design):
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"wmask_out_{}".format(bit),
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"vdd", "gnd"])
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def place_and2_array(self):
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# Place the write mask AND array at the start of each write driver enable length.
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# This ensures the write mask AND array will be directly under the corresponding write driver enable wire.
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@@ -96,56 +88,45 @@ class write_mask_and_array(design.design):
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self.wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
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debug.check(self.wmask_en_len >= self.and2.width,
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"Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,self.wmask_en_len))
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"Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,
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self.wmask_en_len))
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self.width = self.bitcell.width * self.columns
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self.height = self.and2.height
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for i in range(self.num_wmasks):
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base = vector(i * self.wmask_en_len, 0)
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self.and2_insts[i].place(base)
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def add_layout_pins(self):
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# Create the enable pin that connects all write mask AND array's B pins
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beg_en_pin = self.and2_insts[0].get_pin("B")
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end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
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if self.port % 2:
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# Extend metal3 to edge of AND array in multiport
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en_to_edge = self.and2.width - beg_en_pin.cx()
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self.add_layout_pin(text="en",
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layer="m3",
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offset=beg_en_pin.bc(),
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width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge)
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self.add_via_center(layers=self.m1_stack,
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offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
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self.add_via_center(layers=self.m2_stack,
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offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
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else:
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self.add_layout_pin(text="en",
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layer="m3",
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offset=beg_en_pin.bc(),
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width=end_en_pin.cx() - beg_en_pin.cx())
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en_pin = self.and2_insts[0].get_pin("B")
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self.add_layout_pin_segment_center(text="en",
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layer="m3",
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start=vector(0, en_pin.cy()),
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end=vector(self.width, en_pin.cy()))
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for i in range(self.num_wmasks):
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# Copy remaining layout pins
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self.copy_layout_pin(self.and2_insts[i],"A","wmask_in_{0}".format(i))
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self.copy_layout_pin(self.and2_insts[i],"Z","wmask_out_{0}".format(i))
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self.copy_layout_pin(self.and2_insts[i], "A", "wmask_in_{0}".format(i))
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self.copy_layout_pin(self.and2_insts[i], "Z", "wmask_out_{0}".format(i))
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# Add via connections to metal3 for AND array's B pin
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en_pin = self.and2_insts[i].get_pin("B")
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self.add_via_center(layers=self.m1_stack,
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offset=en_pin.center())
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self.add_via_center(layers=self.m2_stack,
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offset=en_pin.center())
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en_pos = en_pin.center()
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer="m3",
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offset=en_pos)
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for supply in ["gnd", "vdd"]:
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supply_pin=self.and2_insts[i].get_pin(supply)
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self.add_power_pin(supply, supply_pin.center())
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for supply in ["gnd", "vdd"]:
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supply_pin_left = self.and2_insts[0].get_pin(supply)
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supply_pin_right = self.and2_insts[self.num_wmasks-1].get_pin(supply)
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self.add_path("m1",[supply_pin_left.lc(), supply_pin_right.rc()])
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supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply)
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self.add_path("m1", [supply_pin_left.lc(), supply_pin_right.rc()])
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def get_cin(self):
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"""Get the relative capacitance of all the input connections in the bank"""
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