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Changes to simplify metal preferred directions and pitches.
Changes to allow decoder height to be a 2x multiple of bitcell height. Split of control logic tests. Fixed track spacing in SRAM and channel router PEP8 cleanup.
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@@ -165,7 +165,7 @@ class write_driver_array(design.design):
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for pin in pin_list:
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self.add_power_pin(name=n,
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loc=pin.center(),
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vertical=True,
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directions=("V", "V"),
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start_layer=pin.layer)
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if self.write_size:
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for bit in range(self.num_wmasks):
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