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singleport cba passing on both tech files

This commit is contained in:
Jesse Cirimelli-Low 2026-03-17 14:50:43 -07:00
parent ffcbd51019
commit b6d98c44d5
2 changed files with 18 additions and 18 deletions
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20
compiler/modules/capped_replica_bitcell_array.py
View File

@ -85,7 +85,8 @@ class capped_replica_bitcell_array(bitcell_base_array):
cols=self.column_size + len(self.rbls), cols=self.column_size + len(self.rbls),
rows=1, rows=1,
# dummy column + left replica column(s) # dummy column + left replica column(s)
column_offset=0, column_offset=1,
row_offset=self.row_size+ self.extra_rows,
mirror=0, mirror=0,
location="top", location="top",
left_rbl=self.left_rbl, left_rbl=self.left_rbl,
@ -95,8 +96,9 @@ class capped_replica_bitcell_array(bitcell_base_array):
cols=self.column_size + len(self.rbls), cols=self.column_size + len(self.rbls),
rows=1, rows=1,
# dummy column + left replica column(s) # dummy column + left replica column(s)
column_offset=0, column_offset=1,
mirror=0, row_offset=0,
mirror=(1+self.row_size+self.extra_rows) % 2,
location="bottom", location="bottom",
left_rbl=self.left_rbl, left_rbl=self.left_rbl,
right_rbl=self.right_rbl) right_rbl=self.right_rbl)
@ -106,20 +108,16 @@ class capped_replica_bitcell_array(bitcell_base_array):
self.row_cap_left = factory.create(module_type=row_cap_module_type, self.row_cap_left = factory.create(module_type=row_cap_module_type,
cols=1, cols=1,
column_offset=0,
row_offset=len(self.left_rbl)+len(self.right_rbl),
rows=self.row_size + self.extra_rows, rows=self.row_size + self.extra_rows,
column_offset=0,
row_offset=0,
location="left") location="left")
self.row_cap_right = factory.create(module_type=row_cap_module_type, self.row_cap_right = factory.create(module_type=row_cap_module_type,
cols=1, cols=1,
# dummy column
# + left replica column(s)
# + bitcell columns
# + right replica column(s)
column_offset=len(self.left_rbl) + self.column_size + self.rbl[0],
row_offset=len(self.left_rbl)+len(self.right_rbl),
rows=self.row_size + self.extra_rows, rows=self.row_size + self.extra_rows,
column_offset=1 + len(self.left_rbl) + self.column_size + len(self.right_rbl),
row_offset=0,
location="right") location="right")
def add_pins(self): def add_pins(self):

16
technology/sky130/custom/sky130_col_cap_array.py
View File

@ -18,7 +18,7 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
""" """
Generate a dummy row/column for the replica array. Generate a dummy row/column for the replica array.
""" """
def __init__(self, rows, cols, column_offset=0, mirror=0, location="", name="", left_rbl=[],right_rbl=[]): def __init__(self, rows, cols, column_offset=0, row_offset=0, mirror=0, location="", name="", left_rbl=[],right_rbl=[]):
self.left_rbl = left_rbl self.left_rbl = left_rbl
self.right_rbl = right_rbl self.right_rbl = right_rbl
super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name, left_rbl=left_rbl, right_rbl=right_rbl) super().__init__(rows, cols, column_offset=column_offset, mirror=mirror, location=location, name=name, left_rbl=left_rbl, right_rbl=right_rbl)
@ -42,15 +42,17 @@ class sky130_col_cap_array(col_cap_array, sky130_bitcell_base_array):
self.cell_inst={} self.cell_inst={}
if self.location == "top": if self.location == "top":
bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \ bit_row = [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \
+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)] \
+ [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True)] \
+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\ + [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False)]\
+ [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="MY")] \
+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False)]
elif self.location == "bottom": elif self.location == "bottom":
bit_row = [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True, mirror="MX")] \ bit_row = [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="XY")] \
+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False, mirror="MX")] \
+ [geometry.instance("00_colend", mod=self.colend1, is_bitcell=True, mirror="MX")] \
+ [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False, mirror="MX")]\ + [geometry.instance("01_strap_p_cent", mod=self.colend2, is_bitcell=False, mirror="MX")]\
+ [geometry.instance("02_colend", mod=self.colend1, is_bitcell=True, mirror="XY")] \
+ [geometry.instance("03_strap_p", mod=self.colend3, is_bitcell=False, mirror="MX")]
bit_row = pattern.rotate_list(bit_row, self.column_offset * 2) bit_row = pattern.rotate_list(bit_row, self.column_offset * 2)
bit_block = [] bit_block = []