luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix width of replica routes. Don't enclose pins if they overlap sufficiently.

Browse Source
This commit is contained in:
mrg
2022-05-09 11:44:46 -07:00
parent 50045e54e8
commit b6c3580e24
3 changed files with 37 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/replica_bitcell_array.py
+10 -2
View File
@@ -6,6 +6,7 @@
import debug
from bitcell_base_array import bitcell_base_array
from contact import contact
from tech import drc, spice, preferred_directions
from tech import cell_properties as props
from vector import vector
@@ -588,6 +589,9 @@ class replica_bitcell_array(bitcell_base_array):
top_loc = vector(self.width + offset_multiple * self.vertical_pitch, self.height)
layer = self.supply_stack[2]
top_via = contact(layer_stack=self.supply_stack,
directions=("H", "H"))
# self.add_layout_pin_rect_ends(text=name,
# layer=layer,
@@ -596,7 +600,8 @@ class replica_bitcell_array(bitcell_base_array):
self.add_layout_pin_segment_center(text=name,
layer=layer,
start=bot_loc,
end=top_loc)
end=top_loc,
width=top_via.second_layer_width)
return (bot_loc, top_loc)
@@ -612,6 +617,8 @@ class replica_bitcell_array(bitcell_base_array):
right_loc = vector(self.width, self.height + offset_multiple * self.horizontal_pitch)
layer = self.supply_stack[0]
side_via = contact(layer_stack=self.supply_stack,
directions=("V", "V"))
# self.add_layout_pin_rect_ends(text=name,
# layer=layer,
@@ -620,7 +627,8 @@ class replica_bitcell_array(bitcell_base_array):
self.add_layout_pin_segment_center(text=name,
layer=layer,
start=left_loc,
end=right_loc)
end=right_loc,
width=side_via.first_layer_height)
return (left_loc, right_loc)