luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'dev' into automated_analytical_model

Browse Source
This commit is contained in:
Hunter Nichols
2021-05-26 18:42:24 -07:00
parent a53c6c51ed 61221ff4fa
commit b3bcf48d2e
14 changed files with 386 additions and 116 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/sram/sram_1bank.py
+3
View File
@@ -326,6 +326,9 @@ class sram_1bank(sram_base):
# they might create some blockages
self.add_layout_pins()
# Some technologies have an isolation
self.add_dnwell(inflate=2)
# Route the pins to the perimeter
if OPTS.perimeter_pins:
self.route_escape_pins()
compiler/sram/sram_base.py
+37 -44
View File
@@ -15,6 +15,7 @@ from design import design
from verilog import verilog
from lef import lef
from sram_factory import factory
from tech import spice, layer
class sram_base(design, verilog, lef):
@@ -81,8 +82,20 @@ class sram_base(design, verilog, lef):
for bit in range(self.word_size + self.num_spare_cols):
self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
# Standard supply and ground names
try:
self.vdd_name = spice["power"]
except KeyError:
self.vdd_name = "vdd"
try:
self.gnd_name = spice["ground"]
except KeyError:
self.gnd_name = "gnd"
self.add_pin(self.vdd_name, "POWER")
self.add_pin(self.gnd_name, "GROUND")
self.ext_supplies = [self.vdd_name, self.gnd_name]
self.ext_supply = {"vdd" : self.vdd_name, "gnd" : self.gnd_name}
def add_global_pex_labels(self):
"""
@@ -224,7 +237,7 @@ class sram_base(design, verilog, lef):
# This will either be used to route or left unconnected.
for pin_name in ["vdd", "gnd"]:
for inst in self.insts:
self.copy_power_pins(inst, pin_name)
self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name])
try:
from tech import power_grid
@@ -234,42 +247,21 @@ class sram_base(design, verilog, lef):
# Route a M3/M4 grid
grid_stack = self.m3_stack
# lowest_coord = self.find_lowest_coords()
# highest_coord = self.find_highest_coords()
# # Add two rails to the side
# if OPTS.route_supplies == "side":
# supply_pins = {}
# # Find the lowest leftest pin for vdd and gnd
# for (pin_name, pin_index) in [("vdd", 0), ("gnd", 1)]:
# pin_width = 8 * getattr(self, "{}_width".format(grid_stack[2]))
# pin_space = 2 * getattr(self, "{}_space".format(grid_stack[2]))
# supply_pitch = pin_width + pin_space
# # Add side power rails on left from bottom to top
# # These have a temporary name and will be connected later.
# # They are here to reserve space now and ensure other pins go beyond
# # their perimeter.
# supply_height = highest_coord.y - lowest_coord.y
# supply_pins[pin_name] = self.add_layout_pin(text=pin_name,
# layer=grid_stack[2],
# offset=lowest_coord + vector(pin_index * supply_pitch, 0),
# width=pin_width,
# height=supply_height)
if not OPTS.route_supplies:
# Do not route the power supply (leave as must-connect pins)
return
elif OPTS.route_supplies == "grid":
from supply_grid_router import supply_grid_router as router
rtr=router(grid_stack, self)
else:
from supply_tree_router import supply_tree_router as router
rtr=router(grid_stack,
self,
pin_type=OPTS.route_supplies)
rtr=router(grid_stack, self, side_pin=(OPTS.route_supplies == "side"))
rtr.route()
if OPTS.route_supplies == "side":
if OPTS.route_supplies in ["left", "right", "top", "bottom", "ring"]:
# Find the lowest leftest pin for vdd and gnd
for pin_name in ["vdd", "gnd"]:
# Copy the pin shape(s) to rectangles
@@ -282,13 +274,14 @@ class sram_base(design, verilog, lef):
# Remove the pin shape(s)
self.remove_layout_pin(pin_name)
# Get the lowest, leftest pin
pin = rtr.get_ll_pin(pin_name)
self.add_layout_pin(pin_name,
pin.layer,
pin.ll(),
pin.width(),
pin.height())
# Get new pins
pins = rtr.get_new_pins(pin_name)
for pin in pins:
self.add_layout_pin(self.ext_supply[pin_name],
pin.layer,
pin.ll(),
pin.width(),
pin.height())
elif OPTS.route_supplies:
# Update these as we may have routed outside the region (perimeter pins)
@@ -319,7 +312,7 @@ class sram_base(design, verilog, lef):
route_width,
pin.height())
self.add_layout_pin(pin_name,
self.add_layout_pin(self.ext_supply[pin_name],
pin.layer,
pin_offset,
pin_width,
@@ -571,7 +564,7 @@ class sram_base(design, verilog, lef):
temp.append("bank_spare_wen{0}[{1}]".format(port, bit))
for port in self.all_ports:
temp.append("wl_en{0}".format(port))
temp.extend(["vdd", "gnd"])
temp.extend(self.ext_supplies)
self.connect_inst(temp)
return self.bank_insts[-1]
@@ -620,7 +613,7 @@ class sram_base(design, verilog, lef):
inputs.append("addr{}[{}]".format(port, bit + self.col_addr_size))
outputs.append("a{}[{}]".format(port, bit + self.col_addr_size))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
return insts
@@ -638,7 +631,7 @@ class sram_base(design, verilog, lef):
inputs.append("addr{}[{}]".format(port, bit))
outputs.append("a{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
return insts
@@ -660,7 +653,7 @@ class sram_base(design, verilog, lef):
inputs.append("din{}[{}]".format(port, bit))
outputs.append("bank_din{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
return insts
@@ -682,7 +675,7 @@ class sram_base(design, verilog, lef):
inputs.append("wmask{}[{}]".format(port, bit))
outputs.append("bank_wmask{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
return insts
@@ -704,7 +697,7 @@ class sram_base(design, verilog, lef):
inputs.append("spare_wen{}[{}]".format(port, bit))
outputs.append("bank_spare_wen{}[{}]".format(port, bit))
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(inputs + outputs + ["clk_buf{}".format(port)] + self.ext_supplies)
return insts
@@ -735,7 +728,7 @@ class sram_base(design, verilog, lef):
if port in self.write_ports:
temp.append("w_en{}".format(port))
temp.append("p_en_bar{}".format(port))
temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port)] + self.ext_supplies)
self.connect_inst(temp)
return insts