Hard cells can accept height parameter too.

compiler/custom/and2_dec.py

@@ -7,34 +7,37 @@
 #
 import debug
 from vector import vector
-import pgate
+import design
 from sram_factory import factory
 from globals import OPTS
+from tech import layer
 
 
-class pand2_dec(pgate.pgate):
+class and2_dec(design.design):
     """
     This is an AND with configurable drive strength.
     """
     def __init__(self, name, size=1, height=None, add_wells=True):
-        debug.info(1, "Creating pand2_dec {}".format(name))
+        
+        design.design.__init__(self, name)
+        
+        debug.info(1, "Creating and2_dec {}".format(name))
         self.add_comment("size: {}".format(size))
-
         self.size = size
-
+        self.height = height
-        pgate.pgate.__init__(self, name, height, add_wells)
+        
-
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
+        
     def create_netlist(self):
         self.add_pins()
         self.create_modules()
         self.create_insts()
 
     def create_modules(self):
-        if OPTS.tech_name == "s8":
+        self.nand = factory.create(module_type="nand2_dec",
-            self.nand = factory.create(module_type="nand2_dec")
+                                   height=self.height)
-        else:
-            self.nand = factory.create(module_type="nand2_dec",
-                                       height=self.height)
             
         self.inv = factory.create(module_type="inv_dec",
                                   height=self.height,
@@ -44,7 +47,13 @@ class pand2_dec(pgate.pgate):
         self.add_mod(self.inv)
         
     def create_layout(self):
+
+        if "li" in layer:
+            self.route_layer = "li"
+        else:
+            self.route_layer = "m1"
         self.width = self.nand.width + self.inv.width
+        self.height = self.nand.height
             
         self.place_insts()
         self.add_wires()

compiler/custom/and3_dec.py

@@ -7,22 +7,26 @@
 #
 import debug
 from vector import vector
-import pgate
+import design
 from sram_factory import factory
 from globals import OPTS
+from tech import layer
 
 
-class pand3_dec(pgate.pgate):
+class and3_dec(design.design):
     """
     This is an AND with configurable drive strength.
     """
     def __init__(self, name, size=1, height=None, add_wells=True):
-        debug.info(1, "Creating pand3_dec {}".format(name))
+        design.design.__init__(self, name)
+        debug.info(1, "Creating and3_dec {}".format(name))
         self.add_comment("size: {}".format(size))
-
         self.size = size
+        self.height = height
         
-        pgate.pgate.__init__(self, name, height, add_wells)
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
 
     def create_netlist(self):
         self.add_pins()
@@ -30,11 +34,8 @@ class pand3_dec(pgate.pgate):
         self.create_insts()
 
     def create_modules(self):
-        if OPTS.tech_name == "s8":
+        self.nand = factory.create(module_type="nand3_dec",
-            self.nand = factory.create(module_type="nand3_dec")
+                                   height=self.height)
-        else:
-            self.nand = factory.create(module_type="nand3_dec",
-                                       height=self.height)
 
         self.inv = factory.create(module_type="inv_dec",
                                   height=self.height,
@@ -44,8 +45,14 @@ class pand3_dec(pgate.pgate):
         self.add_mod(self.inv)
 
     def create_layout(self):
-        self.width = self.nand.width + self.inv.width
+        if "li" in layer:
+            self.route_layer = "li"
+        else:
+            self.route_layer = "m1"
 
+        self.width = self.nand.width + self.inv.width
+        self.height = self.nand.height
+        
         self.place_insts()
         self.add_wires()
         self.add_layout_pins()

compiler/custom/and4_dec.py

@@ -7,22 +7,28 @@
 #
 import debug
 from vector import vector
-import pgate
+import design
 from sram_factory import factory
 from globals import OPTS
+from tech import layer
 
 
-class pand4_dec(pgate.pgate):
+class and4_dec(design.design):
     """
     This is an AND with configurable drive strength.
     """
     def __init__(self, name, size=1, height=None, add_wells=True):
-        debug.info(1, "Creating pand4_dec {}".format(name))
-        self.add_comment("size: {}".format(size))
-
-        self.size = size
         
-        pgate.pgate.__init__(self, name, height, add_wells)
+        design.design.__init__(self, name)
+        
+        debug.info(1, "Creating and4_dec {}".format(name))
+        self.add_comment("size: {}".format(size))
+        self.size = size
+        self.height = height
+        
+        self.create_netlist()
+        if not OPTS.netlist_only:
+            self.create_layout()
 
     def create_netlist(self):
         self.add_pins()
@@ -30,20 +36,24 @@ class pand4_dec(pgate.pgate):
         self.create_insts()
 
     def create_modules(self):
-        if OPTS.tech_name == "s8":
+        self.nand = factory.create(module_type="nand4_dec",
-            self.nand = factory.create(module_type="nand4_dec")
+                                   height=self.height)
-        else:
-            self.nand = factory.create(module_type="nand4_dec",
-                                       height=self.height)
 
         self.inv = factory.create(module_type="inv_dec",
+                                  height=self.height,
                                   size=self.size)
 
         self.add_mod(self.nand)
         self.add_mod(self.inv)
 
     def create_layout(self):
+        if "li" in layer:
+            self.route_layer = "li"
+        else:
+            self.route_layer = "m1"
+
         self.width = self.nand.width + self.inv.width
+        self.height = self.nand.height
 
         self.place_insts()
         self.add_wires()

compiler/custom/nand2_dec.py

@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import design
-from tech import GDS, layer, spice, parameter
+from tech import GDS, layer, spice, parameter, drc
 import logical_effort
 import utils
 
@@ -31,6 +31,14 @@ class nand2_dec(design.design):
         self.height = nand2_dec.height
         self.pin_map = nand2_dec.pin_map
         self.add_pin_types(self.type_list)
+
+        # FIXME: For now...
+        size = 1
+        self.size = size
+        self.nmos_size = 2 * size
+        self.pmos_size = parameter["beta"] * size
+        self.nmos_width = self.nmos_size * drc("minwidth_tx")
+        self.pmos_width = self.pmos_size * drc("minwidth_tx")
         
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""

compiler/custom/nand3_dec.py

@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import design
-from tech import GDS, layer, spice, parameter
+from tech import GDS, layer, spice, parameter, drc
 import logical_effort
 import utils
 
@@ -31,6 +31,14 @@ class nand3_dec(design.design):
         self.height = nand3_dec.height
         self.pin_map = nand3_dec.pin_map
         self.add_pin_types(self.type_list)
+
+        # FIXME: For now...
+        size = 1
+        self.size = size
+        self.nmos_size = 2 * size
+        self.pmos_size = parameter["beta"] * size
+        self.nmos_width = self.nmos_size * drc("minwidth_tx")
+        self.pmos_width = self.pmos_size * drc("minwidth_tx")
         
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""

compiler/custom/nand4_dec.py

@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 import design
-from tech import GDS, layer, spice, parameter
+from tech import GDS, layer, spice, parameter, drc
 import logical_effort
 import utils
 
@@ -31,6 +31,14 @@ class nand4_dec(design.design):
         self.height = nand4_dec.height
         self.pin_map = nand4_dec.pin_map
         self.add_pin_types(self.type_list)
+
+        # FIXME: For now...
+        size = 1
+        self.size = size
+        self.nmos_size = 2 * size
+        self.pmos_size = parameter["beta"] * size
+        self.nmos_width = self.nmos_size * drc("minwidth_tx")
+        self.pmos_width = self.pmos_size * drc("minwidth_tx")
         
     def analytical_power(self, corner, load):
         """Returns dynamic and leakage power. Results in nW"""

compiler/modules/hierarchical_decoder.py

@@ -57,21 +57,15 @@ class hierarchical_decoder(design.design):
         self.DRC_LVS()
                 
     def add_modules(self):
-        if OPTS.tech_name == "s8":
+        self.and2 = factory.create(module_type="and2_dec",
-            self.and2 = factory.create(module_type="pand2_dec")
+                                   height=self.cell_height)
-        else:
-            self.and2 = factory.create(module_type="pand2_dec",
-                                       height=self.cell_height)
         self.add_mod(self.and2)
-        if OPTS.tech_name == "s8":
+        
-            self.and3 = factory.create(module_type="pand3_dec")
+        self.and3 = factory.create(module_type="and3_dec",
-        else:
+                                   height=self.cell_height)
-            self.and3 = factory.create(module_type="pand3_dec",
-                                       height=self.cell_height)
-            
         self.add_mod(self.and3)
         # TBD
-        # self.and4 = factory.create(module_type="pand4_dec")
+        # self.and4 = factory.create(module_type="and4_dec")
         # self.add_mod(self.and4)
         
         self.add_decoders()
@@ -180,6 +174,7 @@ class hierarchical_decoder(design.design):
         # Two extra pitches between modules on left and right
         self.internal_routing_width = self.total_number_of_predecoder_outputs * self.bus_pitch + self.bus_pitch
         self.row_decoder_height = self.and2.height * self.num_outputs
+
         # Extra bus space for supply contacts
         self.input_routing_width = self.num_inputs * self.bus_pitch + self.bus_space
 

compiler/modules/hierarchical_predecode.py

@@ -42,13 +42,13 @@ class hierarchical_predecode(design.design):
 
         # FIXME: Default parms are required for hard cells for now.
         if self.number_of_inputs == 2:
-            self.and_mod = factory.create(module_type="pand2_dec",
+            self.and_mod = factory.create(module_type="and2_dec",
                                           height=self.cell_height)
         elif self.number_of_inputs == 3:
-            self.and_mod = factory.create(module_type="pand3_dec",
+            self.and_mod = factory.create(module_type="and3_dec",
                                           height=self.cell_height)
         elif self.number_of_inputs == 4:
-            self.and_mod = factory.create(module_type="pand4_dec",
+            self.and_mod = factory.create(module_type="and4_dec",
                                           height=self.cell_height)
         else:
             debug.error("Invalid number of predecode inputs: {}".format(self.number_of_inputs), -1)

compiler/pgates/wordline_driver.py

@@ -40,12 +40,8 @@ class wordline_driver(design.design):
         self.create_insts()
 
     def create_modules(self):
-        if OPTS.tech_name == "s8":
+        self.nand = factory.create(module_type="nand2_dec",
-            self.nand = factory.create(module_type="nand2_dec")
+                                   height=self.height)
-            self.height = self.nand.height
-        else:
-            self.nand = factory.create(module_type="nand2_dec",
-                                       height=self.height)
             
         self.driver = factory.create(module_type="inv_dec",
                                      size=self.size,

compiler/tests/04_and2_dec_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class pand3_dec_test(openram_test):
+class and2_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,10 +23,10 @@ class pand3_dec_test(openram_test):
         global verify
         import verify
 
-        import pand3_dec
+        import and2_dec
 
-        debug.info(2, "Testing pand3 gate 4x")
+        debug.info(2, "Testing and2 gate 4x")
-        a = pand3_dec.pand3_dec(name="pand3x4", size=4)
+        a = and2_dec.and2_dec(name="and2x4", size=4)
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/04_and3_dec_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class pand3_dec_test(openram_test):
+class and3_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,10 +23,10 @@ class pand3_dec_test(openram_test):
         global verify
         import verify
 
-        import pand3_dec
+        import and3_dec
 
-        debug.info(2, "Testing pand3 gate 4x")
+        debug.info(2, "Testing and3 gate 4x")
-        a = pand3_dec.pand3_dec(name="pand3x4", size=4)
+        a = and3_dec.and3_dec(name="and3x4", size=4)
         self.local_check(a)
 
         globals.end_openram()

compiler/tests/04_and4_dec_test.py

@@ -15,7 +15,7 @@ from globals import OPTS
 from sram_factory import factory
 import debug
 
-class pand2_dec_test(openram_test):
+class and3_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@@ -23,10 +23,10 @@ class pand2_dec_test(openram_test):
         global verify
         import verify
 
-        import pand2_dec
+        import and3_dec
 
-        debug.info(2, "Testing pand2 gate 4x")
+        debug.info(2, "Testing and3 gate 4x")
-        a = pand2_dec.pand2_dec(name="pand2x4", size=4)
+        a = and3_dec.and3_dec(name="and3x4", size=4)
         self.local_check(a)
 
         globals.end_openram()