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Fixed issue with wire resistance in total resistance equations for cacti. Fixed issue with sense amp resistance values.

This commit is contained in:
Hunter Nichols 2021-08-04 16:10:27 -07:00
parent 134bf573ec
commit b3500982ca
2 changed files with 3 additions and 3 deletions
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2
compiler/base/hierarchy_spice.py
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@ -429,7 +429,7 @@ class spice():
c_wire = self.module_wire_c() c_wire = self.module_wire_c()
r_wire = self.module_wire_r() r_wire = self.module_wire_r()
# Calculate tau with provided output load then calc delay # Calculate tau with provided output load then calc delay
tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_load/2) tf = rd*(c_intrinsic+c_load+c_wire)+r_wire*(c_load+c_wire/2)
this_delay = self.horowitz(inrisetime, tf, 0.5, 0.5, True) this_delay = self.horowitz(inrisetime, tf, 0.5, 0.5, True)
inrisetime = this_delay / (1.0 - 0.5) inrisetime = this_delay / (1.0 - 0.5)
return delay_data(this_delay, inrisetime) return delay_data(this_delay, inrisetime)

4
compiler/custom/sense_amp.py
View File

@ -82,9 +82,9 @@ class sense_amp(design.design):
def get_on_resistance(self): def get_on_resistance(self):
"""On resistance of pinv, defined by single nmos""" """On resistance of pinv, defined by single nmos"""
is_nchannel = False is_nchannel = True
stack = 1 stack = 1
is_cell = False is_cell = False
return self.tr_r_on(parameter["sa_inv_nmos_size"], is_nchannel, stack, is_cell) return self.tr_r_on(parameter["sa_inv_nmos_size"], is_nchannel, stack, is_cell)
def get_input_capacitance(self): def get_input_capacitance(self):