mirror of https://github.com/VLSIDA/OpenRAM.git
Add draft of path exclusion calls
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@ -268,3 +268,35 @@ class global_bitcell_array(bitcell_base_array.bitcell_base_array):
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offsets.extend(inst.lx() + x for x in inst.mod.get_column_offsets())
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offsets.extend(inst.lx() + x for x in inst.mod.get_column_offsets())
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return offsets
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return offsets
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def graph_exclude_bits(self, targ_row, targ_col):
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"""
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Excludes bits in column from being added to graph except target
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"""
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# This must find which local array includes the specified column
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# Find the summation of columns that is large and take the one before
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for i, col in enumerate(self.col_offsets):
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if col > targ_col:
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break
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# We must also translate the global array column number to the local array column number
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self.local_mods[i - 1].graph_exclude_bits(targ_row, targ_col - self.col_offsets[i - 1])
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def graph_exclude_replica_col_bits(self):
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"""
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Exclude all but replica in every local array.
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"""
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for mod in self.local_mods:
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mod.graph_exclude_replica_col_bits()
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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# This must find which local array includes the specified column
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# Find the summation of columns that is large and take the one before
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for i, local_col in enumerate(self.col_offsets):
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if local_col > col:
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break
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return self.local_mods[i - 1].get_cell_name(inst_name + '.x' + self.local_insts[i - 1].name, row, col)
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@ -263,3 +263,20 @@ class local_bitcell_array(bitcell_base_array.bitcell_base_array):
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offsets = [self.bitcell_array_inst.lx() + x for x in self.bitcell_array.get_column_offsets()]
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offsets = [self.bitcell_array_inst.lx() + x for x in self.bitcell_array.get_column_offsets()]
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return offsets
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return offsets
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def graph_exclude_bits(self, targ_row, targ_col):
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"""
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Excludes bits in column from being added to graph except target
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"""
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self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
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def graph_exclude_replica_col_bits(self):
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"""
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Exclude all but replica in the local array.
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"""
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self.bitcell_array.graph_exclude_replica_col_bits()
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def get_cell_name(self, inst_name, row, col):
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"""Gets the spice name of the target bitcell."""
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return self.bitcell_array.get_cell_name(inst_name + '.x' + self.bitcell_array_inst.name, row, col)
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