ROM binary file support

README.md

@@ -60,7 +60,7 @@ OpenRAM is licensed under the [BSD 3-Clause License](./LICENSE).
 + [E. Ebrahimi, M. Guthaus, J. Renau, “Timing Speculative SRAM”, IEEE In- ternational Symposium on Circuits and Systems (ISCAS), 2017.](https://escholarship.org/content/qt7nn0j5x3/qt7nn0j5x3_noSplash_172457455e1aceba20694c3d7aa489b4.pdf)
 + [B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization",  IEEE International Symposium on Circuits and Systems (ISCAS), 2019.](https://escholarship.org/content/qt98s4c1hp/qt98s4c1hp_noSplash_753dcc3e218f60aafff98ef77fb56384.pdf)
 + [B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://ieeexplore.ieee.org/document/8920325)
-+ [H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.](https://escholarship.org/content/qt7047n3k0/qt7047n3k0.pdf?t=q4gcij)
++ [H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control", IFIP/IEEE International Conference on Very Large Scale Integration (VLhttps://www.youtube.com/watch?v=rd5j8mG24H4&t=0sSI-SoC), 2019.](https://escholarship.org/content/qt7047n3k0/qt7047n3k0.pdf?t=q4gcij)
 + [H. Nichols, "Statistical Modeling of SRAMs", M.S. Thesis, UCSC, 2022.](https://escholarship.org/content/qt7vx9n089/qt7vx9n089_noSplash_cfc4ba479d8eb1b6ec25d7c92357bc18.pdf?t=ra9wzr)
 + [M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software", IEEE International Electron Devices Meeting (IEDM), 2020.](https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9372047)
 
@@ -70,7 +70,7 @@ OpenRAM is licensed under the [BSD 3-Clause License](./LICENSE).
 
 - [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
 - [James Stine] from [VLSIARCH] co-founded the project.
-- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera
+- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera, Sage Walker
 
 If I forgot to add you, please let me know!
 

compiler/options.py

@@ -58,6 +58,7 @@ class options(optparse.Values):
     ###################
     rom_endian = "little"
     rom_data = None
+    data_type = "bin"
     strap_spacing = 8
     scramble_bits = True
 

compiler/rom.py

@@ -26,7 +26,8 @@ class rom():
                                 words_per_row=OPTS.words_per_row,
                                 rom_endian=OPTS.rom_endian,
                                 scramble_bits=OPTS.scramble_bits,
-                                strap_spacing=OPTS.strap_spacing)
+                                strap_spacing=OPTS.strap_spacing,
+                                data_type=OPTS.data_type)
 
         if name is None:
             name = OPTS.output_name

compiler/rom_config.py

@@ -16,14 +16,14 @@ from openram import OPTS
 class rom_config:
     """ This is a structure that is used to hold the ROM configuration options. """
 
-    def __init__(self, word_size, rom_data, words_per_row=None, rom_endian="little", scramble_bits=True, strap_spacing=8):
+    def __init__(self, word_size, rom_data, words_per_row=None, rom_endian="little", scramble_bits=True, strap_spacing=8, data_type="hex"):
         self.word_size = word_size
         self.word_bits = self.word_size * 8
         self.rom_data = rom_data
         self.strap_spacing = strap_spacing
         # TODO: This currently does nothing. It should change the behavior of the chunk funciton.
         self.endian = rom_endian
-
+        self.data_type = data_type
         # This should pretty much always be true. If you want to make silicon art you might set to false
         self.scramble_bits = scramble_bits
         # This will get over-written when we determine the organization
@@ -57,18 +57,12 @@ class rom_config:
     def compute_sizes(self):
         """  Computes the organization of the memory using data size by trying to make it a rectangle."""
 
-        # Read data as hexidecimal text file
+        if self.data_type == "hex":
-        hex_file = open(self.rom_data, 'r')
+            raw_data = self.read_data_hex()
-        hex_data = hex_file.read()
+        elif self.data_type == "bin":
-
+            raw_data = self.read_data_bin()
-        # Convert from hex into an int
+        else:
-        data_int = int(hex_data, 16)
+            debug.error(f"Invalid input data type: {self.data_type}", -1)
-        # Then from int into a right aligned, zero padded string
-        bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
-
-        # Then turn the string into a list of ints
-        bin_data = list(bin_string)
-        raw_data = [int(x) for x in bin_data]
 
         # data size in bytes
         data_size = len(raw_data) / 8
@@ -93,6 +87,35 @@ class rom_config:
         OPTS.words_per_row = self.words_per_row
         debug.info(1, "Read rom data file: length {0} bytes, {1} words, set number of cols to {2}, rows to {3}, with {4} words per row".format(data_size, self.num_words, self.cols, self.rows, self.words_per_row))
 
+    def read_data_hex(self) -> List[int]:
+        # Read data as hexidecimal text file
+        with open(self.rom_data, 'r') as hex_file:
+            hex_data = hex_file.read()
+
+        # Convert from hex into an int
+        data_int = int(hex_data, 16)
+        # Then from int into a right aligned, zero padded string
+        bin_string = bin(data_int)[2:].zfill(len(hex_data) * 4)
+
+        # Then turn the string into a list of ints
+        bin_data = list(bin_string)
+        raw_data = [int(x) for x in bin_data]
+        return raw_data
+
+    def read_data_bin(self) -> List[int]:
+
+        # Read data as a binary file
+        with open(self.rom_data, 'rb') as bin_file:
+            bin_data = bin_file.read()
+
+        # Convert from a list of bytes to a single string of bits
+        bin_string = "".join(f"{n:08b}" for n in bin_data)
+
+        # Then turn the string into a list of ints
+        bin_data = list(bin_string)
+        raw_data = [int(x) for x in bin_data]
+        return raw_data
+
 
     def chunk_data(self, raw_data: List[int]):
         """

docs/source/index.md

@@ -108,10 +108,11 @@ Commercial tools (optional):
     * Michael Grimes
     * Jennifer Sowash
     * Jesse Cirimelli-Low
-    <img align="right" height="100" src="../assets/images/logos/vlsida.png">
+    <img align="right" height="100" src="../assets/images/logos/vlsida.png">https://www.youtube.com/watch?v=rd5j8mG24H4&t=0s
 * Many other past students:
     * Jeff Butera
     * Tom Golubev
     * Marcelo Sero
     * Seokjoong Kim
+    * Sage Walker
 

macros/rom_configs/sky130_rom_1kbyte.py

@@ -10,7 +10,8 @@ word_size = 1
 
 check_lvsdrc = True
 
-rom_data = "macros/rom_configs/example_1kbyte.dat"
+rom_data = "rom_configs/example_1kbyte.bin"
+data_type = "bin"
 
 output_name = "rom_1kbyte"
 output_path = "macro/{output_name}".format(**locals())