s8 gdsless netlist only working up to dff array

compiler/base/utils.py

@@ -96,10 +96,10 @@ def get_libcell_size(name, units, lpp):
     Open a GDS file and return the library cell size from either the
     bounding box or a border layer.
     """
-    if not OPTS.netlist_only:
+
     cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
     return(get_gds_size(name, cell_gds, units, lpp))
-    return (0,0,)
+
 
 
 def get_gds_pins(pin_names, name, gds_filename, units):
@@ -130,11 +130,9 @@ def get_libcell_pins(pin_list, name, units):
     Open a GDS file and find the pins in pin_list as text on a given layer.
     Return these as a rectangle layer pair for each pin.
     """
-    if not OPTS.netlist_only:
+
     cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
     return(get_gds_pins(pin_list, name, cell_gds, units))
-    else:
-        return
 
 
 

compiler/bitcells/bitcell.py

@@ -81,6 +81,9 @@ class bitcell(bitcell_base.bitcell_base):
 
     def get_wl_name(self, port=0):
         """Get wl name"""
+        if cell_properties.bitcell.split_wl:
+            return "wl{}".format(port)
+        else:
             debug.check(port == 0, "One port for bitcell only.")
             return "wl"
     

compiler/bitcells/replica_bitcell.py

@@ -8,7 +8,8 @@
 import design
 import debug
 import utils
-from tech import GDS,layer,drc,parameter
+from tech import GDS,layer,drc,parameter,cell_properties
+from globals import OPTS
 
 class replica_bitcell(design.design):
     """
@@ -17,10 +18,19 @@ class replica_bitcell(design.design):
     is a hand-made cell, so the layout and netlist should be available in
     the technology library. """
 
+    if cell_properties.bitcell.split_wl:
+        pin_names = ["bl", "br", "wl0", "wl1", "vdd", "gnd"]
+    else:
         pin_names = ["bl", "br", "wl", "vdd", "gnd"]
+
     type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] 
+    
+    if not OPTS.netlist_only:
         (width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"])
         pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"])
+    else:
+        (width,height) = (0,0)
+        pin_map = []
 
     def __init__(self, name=""):
         # Ignore the name argument

compiler/modules/replica_bitcell_array.py

@@ -158,7 +158,7 @@ class replica_bitcell_array(design.design):
         # Left port WLs (one dummy for each port when we allow >1 port)
         for port in range(self.left_rbl):
             # Make names for all RBLs
-            wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.all_ports))]
+            wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))]
             # Keep track of the pin that is the RBL
             self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
             self.replica_col_wl_names.extend(wl_names)
@@ -167,7 +167,7 @@ class replica_bitcell_array(design.design):
         # Right port WLs (one dummy for each port when we allow >1 port)
         for port in range(self.left_rbl,self.left_rbl+self.right_rbl):
             # Make names for all RBLs
-            wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.all_ports))]
+            wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))]
             # Keep track of the pin that is the RBL
             self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
             self.replica_col_wl_names.extend(wl_names)

compiler/modules/sense_amp.py

@@ -9,6 +9,7 @@ import design
 import debug
 import utils
 from tech import GDS,layer, parameter,drc
+from globals import OPTS
 import logical_effort
 
 class sense_amp(design.design):
@@ -21,8 +22,12 @@ class sense_amp(design.design):
 
     pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"]
     type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
+    if not OPTS.netlist_only:
         (width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
         pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
+    else:
+        (width, height) = (0,0)
+        pin_map = []
 
     def __init__(self, name):
         design.design.__init__(self, name)

compiler/modules/write_driver.py

@@ -8,6 +8,7 @@
 import debug
 import design
 import utils
+from globals import OPTS
 from tech import GDS,layer
 
 class write_driver(design.design):
@@ -20,8 +21,12 @@ class write_driver(design.design):
 
     pin_names = ["din", "bl", "br", "en", "vdd", "gnd"]
     type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
+    if not OPTS.netlist_only:
         (width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
         pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
+    else:
+        (width,height) = (0,0)
+        pin_map = []
 
     def __init__(self, name):
         design.design.__init__(self, name)

compiler/sram/sram_config.py

@@ -23,10 +23,7 @@ class sram_config:
         # This will get over-written when we determine the organization
         self.words_per_row = words_per_row
 
-        if not OPTS.netlist_only:
         self.compute_sizes()
-        else:
-            self.compute_simple_sram_sizes()
 
         
 
@@ -39,15 +36,6 @@ class sram_config:
         for member in members:
             setattr(module,member,getattr(self,member))
 
-    def compute_simple_sram_sizes(self):
-        self.row_addr_size = int(log(OPTS.num_words, 2))
-        self.col_addr_size = int(log(OPTS.word_size, 2))
-        self.words_per_row = 1
-        self.num_rows = OPTS.num_words
-        self.num_cols = OPTS.word_size
-        self.bank_addr_size = self.col_addr_size + self.row_addr_size
-        self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
-
     def compute_sizes(self):
         """  Computes the organization of the memory using bitcell size by trying to make it square."""