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s8 gdsless netlist only working up to dff array

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jcirimel
2020-02-09 21:37:09 -08:00
parent b107934672
commit b212b3e85a
7 changed files with 43 additions and 34 deletions
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compiler/modules/replica_bitcell_array.py
+2 -2
View File
@@ -158,7 +158,7 @@ class replica_bitcell_array(design.design):
# Left port WLs (one dummy for each port when we allow >1 port)
for port in range(self.left_rbl):
# Make names for all RBLs
wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.all_ports))]
wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))]
# Keep track of the pin that is the RBL
self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
self.replica_col_wl_names.extend(wl_names)
@@ -167,7 +167,7 @@ class replica_bitcell_array(design.design):
# Right port WLs (one dummy for each port when we allow >1 port)
for port in range(self.left_rbl,self.left_rbl+self.right_rbl):
# Make names for all RBLs
wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.all_ports))]
wl_names=["rbl_{0}_{1}".format(self.cell.get_wl_name(x),port) for x in range(len(self.cell.get_all_wl_names()))]
# Keep track of the pin that is the RBL
self.rbl_wl_names[port]=wl_names[self.bitcell_ports[port]]
self.replica_col_wl_names.extend(wl_names)
compiler/modules/sense_amp.py
+7 -2
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@@ -9,6 +9,7 @@ import design
import debug
import utils
from tech import GDS,layer, parameter,drc
from globals import OPTS
import logical_effort
class sense_amp(design.design):
@@ -21,8 +22,12 @@ class sense_amp(design.design):
pin_names = ["bl", "br", "dout", "en", "vdd", "gnd"]
type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"])
else:
(width, height) = (0,0)
pin_map = []
def __init__(self, name):
design.design.__init__(self, name)
compiler/modules/write_driver.py
+7 -2
View File
@@ -8,6 +8,7 @@
import debug
import design
import utils
from globals import OPTS
from tech import GDS,layer
class write_driver(design.design):
@@ -20,8 +21,12 @@ class write_driver(design.design):
pin_names = ["din", "bl", "br", "en", "vdd", "gnd"]
type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
if not OPTS.netlist_only:
(width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, name):
design.design.__init__(self, name)