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Reimplement off grid pins.

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Long pins aren't accessed on end pins anymore.
Fix problem with multiple non-enclosed space causing blockages.
Add partial pin offgrid enclosure algorithm.
This commit is contained in:
mrg
2022-05-02 15:43:14 -07:00
parent 7195d81736
commit b1bb9151c4
17 changed files with 274 additions and 155 deletions
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compiler/modules/delay_chain.py
+3 -19
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@@ -172,25 +172,9 @@ class delay_chain(design.design):
self.add_path("m2", [z_pin.center(), mid1_point, mid2_point, next_a_pin.center()])
def route_supplies(self):
# Add power and ground to all the cells except:
# the fanout driver, the right-most load
# The routing to connect the loads is over the first and last cells
# We have an even number of drivers and must only do every other
# supply rail
if True or OPTS.experimental_power:
left_load_insts = [self.load_inst_map[x][0] for x in self.driver_inst_list]
right_load_insts = [self.load_inst_map[x][-1] for x in self.driver_inst_list]
self.route_vertical_pins("vdd", left_load_insts, xside="lx")
self.route_vertical_pins("gnd", right_load_insts, xside="rx")
else:
for inst in self.driver_inst_list:
load_list = self.load_inst_map[inst]
for pin_name in ["vdd", "gnd"]:
pin = load_list[0].get_pin(pin_name)
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
pin = load_list[-2].get_pin(pin_name)
self.copy_power_pin(pin, loc=pin.rc() - vector(self.m1_pitch, 0))
self.route_vertical_pins("vdd", self.driver_inst_list, xside="lx")
right_load_insts = [self.load_inst_map[x][-1] for x in self.driver_inst_list]
self.route_vertical_pins("gnd", right_load_insts, xside="rx")
def add_layout_pins(self):