Moved feasible period search from functional.py to tests.

compiler/characterizer/functional.py

@@ -27,7 +27,7 @@ class functional(simulation):
 
         self.set_corner(corner)
         self.set_spice_constants()
-        self.set_feasible_period(sram, spfile, corner)
+        #self.set_feasible_period(sram, spfile, corner)
         self.set_stimulus_variables()
         self.create_signal_names()
 
@@ -38,27 +38,9 @@ class functional(simulation):
         self.write_check = []
         self.read_check = []
     
-    def set_feasible_period(self, sram, spfile, corner):
+    def run(self, feasible_period=None):
-        """Creates a delay simulation to determine a feasible period for the functional tests to run.
+        if feasible_period: #period defaults to tech.py feasible period otherwise.
-           Only determines the feasible period for a single port and assumes that for all ports for performance.
+            self.period = feasible_period
-        """
-        OPTS.trim_netlist = False #This has to be false or the write port will flip a bit in the trimmed netlist.
-        debug.info(1, "Determining feasible period using untrimmed netlist for functional test.")
-        delay_sim = delay(sram, spfile, corner)
-        delay_sim.set_load_slew(self.load,self.slew)
-        delay_sim.set_probe(probe_address="1"*self.addr_size, probe_data=(self.sram.word_size-1))
-        delay_sim.find_feasible_period_one_port(self.read_ports[0]) #Finds feasible and sets internal period
-        self.period = delay_sim.period #copy internal period of delay object here
-    
-    # def set_spice_constants(self):
-        # """Spice constants for functional test"""
-        # simulation.set_spice_constants(self)
-        # #Heuristic increase for functional period. Base feasible period typically does not pass the functional test
-        # #for column mux or srams of this size. Increase the feasible period by 20% for this case.
-        # if self.sram.words_per_row >= 4 or self.sram.num_cols*self.sram.num_rows >= 1024:
-            # self.period = self.period*1.2
-    
-    def run(self):
         # Generate a random sequence of reads and writes
         self.write_random_memory_sequence()
     

compiler/tests/21_hspice_delay_test.py

@@ -52,7 +52,7 @@ class timing_sram_test(openram_test):
         if OPTS.tech_name == "freepdk45":
             golden_data = {'delay_hl': [0.2011],
                          'delay_lh': [0.2011],
-                         'leakage_power': 0.0014218000000000002,
+                         'leakage_power': 0.002,
                          'min_period': 0.41,
                          'read0_power': [0.63604],
                          'read1_power': [0.6120599999999999],

compiler/tests/21_hspice_setuphold_test.py

@@ -33,7 +33,7 @@ class timing_setup_test(openram_test):
         data = sh.analyze(slews,slews)
         #print data
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'hold_times_HL': [-0.0097656],
+            golden_data = {'hold_times_HL': [-0.0158691],
                            'hold_times_LH': [-0.0158691],
                            'setup_times_HL': [0.026855499999999997],
                            'setup_times_LH': [0.032959]}

compiler/tests/22_psram_1bank_2mux_func_test.py

@@ -18,6 +18,7 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.num_rw_ports = 1
@@ -28,7 +29,7 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -47,8 +48,10 @@ class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/22_psram_1bank_4mux_func_test.py

@@ -18,6 +18,7 @@ class psram_1bank_4mux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.num_rw_ports = 1
@@ -28,7 +29,7 @@ class psram_1bank_4mux_func_test(openram_test):
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -47,8 +48,10 @@ class psram_1bank_4mux_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/22_psram_1bank_8mux_func_test.py

@@ -18,6 +18,7 @@ class psram_1bank_8mux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.num_rw_ports = 1
@@ -28,7 +29,7 @@ class psram_1bank_8mux_func_test(openram_test):
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -47,8 +48,10 @@ class psram_1bank_8mux_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/22_psram_1bank_nomux_func_test.py

@@ -18,6 +18,7 @@ class psram_1bank_nomux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell="replica_pbitcell"
         OPTS.num_rw_ports = 1
@@ -28,7 +29,7 @@ class psram_1bank_nomux_func_test(openram_test):
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -47,8 +48,10 @@ class psram_1bank_nomux_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/22_sram_1bank_2mux_func_test.py

@@ -18,12 +18,13 @@ class sram_1bank_2mux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -39,10 +40,12 @@ class sram_1bank_2mux_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
-        (fail, error) = f.run()
+        (fail, error) = f.run(feasible_period)
         self.assertTrue(fail,error)
         
         globals.end_openram()

compiler/tests/22_sram_1bank_4mux_func_test.py

@@ -18,12 +18,13 @@ class sram_1bank_4mux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -39,8 +40,10 @@ class sram_1bank_4mux_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/22_sram_1bank_8mux_func_test.py

@@ -18,12 +18,13 @@ class sram_1bank_8mux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         
         # This is a hack to reload the characterizer __init__ with the spice version
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         if not OPTS.spice_exe:
             debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
 
@@ -39,12 +40,13 @@ class sram_1bank_8mux_func_test(openram_test):
                                                                                                                 c.num_banks))
         s = sram(c, name="sram")
         tempspice = OPTS.openram_temp + "temp.sp"        
-        tempspice = OPTS.openram_temp + "temp.sp"        
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py

@@ -18,6 +18,7 @@ class psram_1bank_nomux_func_test(openram_test):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
+        OPTS.trim_netlist = False
         OPTS.bitcell = "bitcell_1rw_1r"
         OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
         OPTS.num_rw_ports = 1
@@ -28,7 +29,7 @@ class psram_1bank_nomux_func_test(openram_test):
         from importlib import reload
         import characterizer
         reload(characterizer)
-        from characterizer import functional
+        from characterizer import functional, delay
         from sram import sram
         from sram_config import sram_config
         c = sram_config(word_size=4,
@@ -44,8 +45,10 @@ class psram_1bank_nomux_func_test(openram_test):
         s.sp_write(tempspice)
         
         corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
-        
         f = functional(s.s, tempspice, corner)
+        d = delay(s.s, tempspice, corner)
+        feasible_period = self.find_feasible_test_period(d, s.s, f.load, f.slew)
+        
         f.num_cycles = 10
         (fail, error) = f.run()
         self.assertTrue(fail,error)

compiler/tests/testutils.py

@@ -54,6 +54,17 @@ class openram_test(unittest.TestCase):
         if OPTS.purge_temp:
             self.cleanup()
 
+    def find_feasible_test_period(self, delay_obj, sram, load, slew):
+        """Creates a delay simulation to determine a feasible period for the functional tests to run.
+           Only determines the feasible period for a single port and assumes that for all ports for performance.
+        """
+        debug.info(1, "Finding feasible period for current test.")
+        delay_obj.set_load_slew(load, slew)
+        delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
+        test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
+        delay_obj.find_feasible_period_one_port(test_port) 
+        return delay_obj.period        
+            
     def cleanup(self):
         """ Reset the duplicate checker and cleanup files. """
         files = glob.glob(OPTS.openram_temp + '*')