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PEP8 formatting

This commit is contained in:
mrg 2020-09-29 16:52:27 -07:00
parent 066570bfeb
commit b147e8485c
6 changed files with 34 additions and 27 deletions
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7
compiler/modules/bank.py
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@ -8,8 +8,8 @@
import debug import debug
import design import design
from sram_factory import factory from sram_factory import factory
from math import log, ceil, floor from math import log, ceil, floor, sqrt
from tech import drc, layer from tech import drc
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
@ -377,7 +377,8 @@ class bank(design.design):
try: try:
local_array_size = OPTS.local_array_size local_array_size = OPTS.local_array_size
except AttributeError: except AttributeError:
local_array_size = 0 #local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
local_array_size = ceil(sqrt(self.num_cols + self.num_spare_cols))
if local_array_size > 0: if local_array_size > 0:
# Find the even multiple that satisfies the fanout with equal sized local arrays # Find the even multiple that satisfies the fanout with equal sized local arrays

3
compiler/options.py
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@ -30,9 +30,6 @@ class options(optparse.Values):
num_r_ports = 0 num_r_ports = 0
num_w_ports = 0 num_w_ports = 0
# By default, use local arrays with a max fanout of 16
#local_array_size = 16
# Write mask size, default will be overwritten with word_size if not user specified # Write mask size, default will be overwritten with word_size if not user specified
write_size = None write_size = None

29
compiler/sram/sram_base.py
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@ -87,8 +87,8 @@ class sram_base(design, verilog, lef):
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT") self.add_pin("dout{0}[{1}]".format(port, bit), "OUTPUT")
self.add_pin("vdd","POWER") self.add_pin("vdd", "POWER")
self.add_pin("gnd","GROUND") self.add_pin("gnd", "GROUND")
def add_global_pex_labels(self): def add_global_pex_labels(self):
""" """
@ -118,8 +118,19 @@ class sram_base(design, verilog, lef):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]] Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]] Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
OPTS.words_per_row = self.words_per_row OPTS.words_per_row = self.words_per_row
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))) , storage_layer_name, Q) row = int(cell % (OPTS.num_words / self.words_per_row))
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num, int(cell % (OPTS.num_words / self.words_per_row)), int(cell / (OPTS.num_words))), storage_layer_name, Q_bar) col = int(cell / (OPTS.num_words))
self.add_layout_pin_rect_center("bitcell_Q_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q))
self.add_layout_pin_rect_center("bitcell_Q_bar_b{}_r{}_c{}".format(bank_num,
row,
col,
storage_layer_name,
Q_bar))
for cell in range(len(bl_offsets)): for cell in range(len(bl_offsets)):
col = bl_meta[cell][0][2] col = bl_meta[cell][0][2]
@ -140,18 +151,14 @@ class sram_base(design, verilog, lef):
self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0]) self.add_layout_pin_rect_center("br{0}_{1}".format(br[i][1], br[i][2]), bitline_layer_name, br[i][0])
# add pex labels for control logic # add pex labels for control logic
for i in range (len(self.control_logic_insts)): for i in range(len(self.control_logic_insts)):
instance = self.control_logic_insts[i] instance = self.control_logic_insts[i]
control_logic_offset = instance.offset control_logic_offset = instance.offset
for output in instance.mod.output_list: for output in instance.mod.output_list:
pin = instance.mod.get_pin(output) pin = instance.mod.get_pin(output)
pin.transform([0,0], instance.mirror, instance.rotate) pin.transform([0, 0], instance.mirror, instance.rotate)
offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]] offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]]
self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), storage_layer_name, offset) self.add_layout_pin_rect_center("{0}{1}".format(pin.name, i), storage_layer_name, offset)
def create_netlist(self): def create_netlist(self):
""" Netlist creation """ """ Netlist creation """

9
compiler/tests/50_riscv_func_test.py
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@ -8,14 +8,15 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
@unittest.skip("SKIPPING 50_riscv_func_test")
# @unittest.skip("SKIPPING 50_riscv_func_test")
class riscv_func_test(openram_test): class riscv_func_test(openram_test):
def runTest(self): def runTest(self):
@ -33,7 +34,7 @@ class riscv_func_test(openram_test):
from importlib import reload from importlib import reload
import characterizer import characterizer
reload(characterizer) reload(characterizer)
from characterizer import functional, delay from characterizer import functional
from sram_config import sram_config from sram_config import sram_config
c = sram_config(word_size=32, c = sram_config(word_size=32,
write_size=8, write_size=8,
@ -53,7 +54,7 @@ class riscv_func_test(openram_test):
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner) f = functional(s.s, tempspice, corner)
(fail, error) = f.run() (fail, error) = f.run()
self.assertTrue(fail,error) self.assertTrue(fail, error)
globals.end_openram() globals.end_openram()

5
compiler/tests/50_riscv_phys_test.py
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@ -8,14 +8,15 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
@unittest.skip("SKIPPING 50_riscv_phys_test")
# @unittest.skip("SKIPPING 50_riscv_phys_test")
class riscv_phys_test(openram_test): class riscv_phys_test(openram_test):
def runTest(self): def runTest(self):