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update to sense amp and write driver modules

This commit is contained in:
Joey Kunzler 2020-03-30 20:00:32 -07:00
parent 9907daaffa
commit b0d2946c80
3 changed files with 33 additions and 28 deletions
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33
compiler/modules/sense_amp_array.py
View File

@ -22,7 +22,7 @@ class sense_amp_array(design.design):
def __init__(self, name, word_size, words_per_row): def __init__(self, name, word_size, words_per_row):
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name)) debug.info(1, "Creating {0}".format(self.name))
self.add_comment("word_size {0}".format(word_size)) self.add_comment("word_size {0}".format(word_size))
self.add_comment("words_per_row: {0}".format(words_per_row)) self.add_comment("words_per_row: {0}".format(words_per_row))
self.word_size = word_size self.word_size = word_size
@ -56,7 +56,7 @@ class sense_amp_array(design.design):
def create_layout(self): def create_layout(self):
self.height = self.amp.height self.height = self.amp.height
if self.bitcell.width > self.amp.width: if self.bitcell.width > self.amp.width:
self.width = self.bitcell.width * self.word_size * self.words_per_row self.width = self.bitcell.width * self.word_size * self.words_per_row
else: else:
@ -76,16 +76,16 @@ class sense_amp_array(design.design):
self.add_pin(self.en_name, "INPUT") self.add_pin(self.en_name, "INPUT")
self.add_pin("vdd", "POWER") self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND") self.add_pin("gnd", "GROUND")
def add_modules(self): def add_modules(self):
self.amp = factory.create(module_type="sense_amp") self.amp = factory.create(module_type="sense_amp")
self.add_mod(self.amp) self.add_mod(self.amp)
# This is just used for measurements, # This is just used for measurements,
# so don't add the module # so don't add the module
self.bitcell = factory.create(module_type="bitcell") self.bitcell = factory.create(module_type="bitcell")
def create_sense_amp_array(self): def create_sense_amp_array(self):
self.local_insts = [] self.local_insts = []
for i in range(0,self.word_size): for i in range(0,self.word_size):
@ -121,11 +121,11 @@ class sense_amp_array(design.design):
amp_position = vector(xoffset, 0) amp_position = vector(xoffset, 0)
self.local_insts[i].place(offset=amp_position,mirror=mirror) self.local_insts[i].place(offset=amp_position,mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):
for i in range(len(self.local_insts)): for i in range(len(self.local_insts)):
inst = self.local_insts[i] inst = self.local_insts[i]
self.add_power_pin(name = "gnd", self.add_power_pin(name = "gnd",
loc = inst.get_pin("gnd").center(), loc = inst.get_pin("gnd").center(),
start_layer="m2", start_layer="m2",
@ -141,40 +141,41 @@ class sense_amp_array(design.design):
dout_pin = inst.get_pin(inst.mod.dout_name) dout_pin = inst.get_pin(inst.mod.dout_name)
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
layer="m2", layer=bl_pin.layer,
offset=bl_pin.ll(), offset=bl_pin.ll(),
width=bl_pin.width(), width=bl_pin.width(),
height=bl_pin.height()) height=bl_pin.height())
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
layer="m2", layer=br_pin.layer,
offset=br_pin.ll(), offset=br_pin.ll(),
width=br_pin.width(), width=br_pin.width(),
height=br_pin.height()) height=br_pin.height())
self.add_layout_pin(text=self.data_name + "_{0}".format(i), self.add_layout_pin(text=self.data_name + "_{0}".format(i),
layer="m2", layer=dout_pin.layer,
offset=dout_pin.ll(), offset=dout_pin.ll(),
width=dout_pin.width(), width=dout_pin.width(),
height=dout_pin.height()) height=dout_pin.height())
def route_rails(self): def route_rails(self):
# add sclk rail across entire array # add sclk rail across entire array
sclk = self.amp.get_pin(self.amp.en_name)
sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1) sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
self.add_layout_pin(text=self.en_name, self.add_layout_pin(text=self.en_name,
layer="m1", layer=sclk.layer,
offset=sclk_offset, offset=sclk_offset,
width=self.width, width=self.width,
height=drc("minwidth_m1")) height=drc("minwidth_" + sclk.layer))
def input_load(self): def input_load(self):
return self.amp.input_load() return self.amp.input_load()
def get_en_cin(self): def get_en_cin(self):
"""Get the relative capacitance of all the sense amp enable connections in the array""" """Get the relative capacitance of all the sense amp enable connections in the array"""
sense_amp_en_cin = self.amp.get_en_cin() sense_amp_en_cin = self.amp.get_en_cin()
return sense_amp_en_cin * self.word_size return sense_amp_en_cin * self.word_size
def get_drain_cin(self): def get_drain_cin(self):
"""Get the relative capacitance of the drain of the PMOS isolation TX""" """Get the relative capacitance of the drain of the PMOS isolation TX"""
from tech import parameter from tech import parameter

18
compiler/modules/write_driver_array.py
View File

@ -23,7 +23,7 @@ class write_driver_array(design.design):
design.design.__init__(self, name) design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name)) debug.info(1, "Creating {0}".format(self.name))
self.add_comment("columns: {0}".format(columns)) self.add_comment("columns: {0}".format(columns))
self.add_comment("word_size {0}".format(word_size)) self.add_comment("word_size {0}".format(word_size))
self.columns = columns self.columns = columns
self.word_size = word_size self.word_size = word_size
@ -57,15 +57,15 @@ class write_driver_array(design.design):
self.add_modules() self.add_modules()
self.add_pins() self.add_pins()
self.create_write_array() self.create_write_array()
def create_layout(self): def create_layout(self):
if self.bitcell.width > self.driver.width: if self.bitcell.width > self.driver.width:
self.width = self.columns * self.bitcell.width self.width = self.columns * self.bitcell.width
else: else:
self.width = self.columns * self.driver.width self.width = self.columns * self.driver.width
self.height = self.driver.height self.height = self.driver.height
self.place_write_array() self.place_write_array()
self.add_layout_pins() self.add_layout_pins()
self.add_boundary() self.add_boundary()
@ -139,26 +139,26 @@ class write_driver_array(design.design):
base = vector(xoffset, 0) base = vector(xoffset, 0)
self.driver_insts[index].place(offset=base, mirror=mirror) self.driver_insts[index].place(offset=base, mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):
for i in range(self.word_size): for i in range(self.word_size):
inst = self.driver_insts[i] inst = self.driver_insts[i]
din_pin = inst.get_pin(inst.mod.din_name) din_pin = inst.get_pin(inst.mod.din_name)
self.add_layout_pin(text=self.data_name + "_{0}".format(i), self.add_layout_pin(text=self.data_name + "_{0}".format(i),
layer="m2", layer=din_pin.layer,
offset=din_pin.ll(), offset=din_pin.ll(),
width=din_pin.width(), width=din_pin.width(),
height=din_pin.height()) height=din_pin.height())
bl_pin = inst.get_pin(inst.mod.get_bl_names()) bl_pin = inst.get_pin(inst.mod.get_bl_names())
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i), self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
layer="m2", layer=bl_pin.layer,
offset=bl_pin.ll(), offset=bl_pin.ll(),
width=bl_pin.width(), width=bl_pin.width(),
height=bl_pin.height()) height=bl_pin.height())
br_pin = inst.get_pin(inst.mod.get_br_names()) br_pin = inst.get_pin(inst.mod.get_br_names())
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i), self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
layer="m2", layer=br_pin.layer,
offset=br_pin.ll(), offset=br_pin.ll(),
width=br_pin.width(), width=br_pin.width(),
height=br_pin.height()) height=br_pin.height())
@ -194,7 +194,7 @@ class write_driver_array(design.design):
width=self.width) width=self.width)
def get_w_en_cin(self): def get_w_en_cin(self):
"""Get the relative capacitance of all the enable connections in the bank""" """Get the relative capacitance of all the enable connections in the bank"""

10
compiler/tests/09_sense_amp_array_test.py
View File

@ -22,6 +22,10 @@ class sense_amp_test(openram_test):
globals.init_openram(config_file) globals.init_openram(config_file)
# check sense amp array for single port # check sense amp array for single port
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
self.local_check(a)
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2") debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2) a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
self.local_check(a) self.local_check(a)
@ -29,7 +33,7 @@ class sense_amp_test(openram_test):
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4") debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a) self.local_check(a)
# check sense amp array for multi-port # check sense amp array for multi-port
OPTS.bitcell = "pbitcell" OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
@ -44,9 +48,9 @@ class sense_amp_test(openram_test):
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)") debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4) a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=4)
self.local_check(a) self.local_check(a)
globals.end_openram() globals.end_openram()
# run the test from the command line # run the test from the command line
if __name__ == "__main__": if __name__ == "__main__":
(OPTS, args) = globals.parse_args() (OPTS, args) = globals.parse_args()