mirror of https://github.com/VLSIDA/OpenRAM.git
update to sense amp and write driver modules
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9907daaffa
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b0d2946c80
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@ -141,18 +141,18 @@ class sense_amp_array(design.design):
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dout_pin = inst.get_pin(inst.mod.dout_name)
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dout_pin = inst.get_pin(inst.mod.dout_name)
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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width=bl_pin.width(),
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height=bl_pin.height())
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height=bl_pin.height())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer="m2",
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layer=br_pin.layer,
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offset=br_pin.ll(),
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offset=br_pin.ll(),
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width=br_pin.width(),
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width=br_pin.width(),
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height=br_pin.height())
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height=br_pin.height())
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer="m2",
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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width=dout_pin.width(),
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height=dout_pin.height())
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height=dout_pin.height())
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@ -160,12 +160,13 @@ class sense_amp_array(design.design):
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def route_rails(self):
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def route_rails(self):
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# add sclk rail across entire array
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# add sclk rail across entire array
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sclk = self.amp.get_pin(self.amp.en_name)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
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sclk_offset = self.amp.get_pin(self.amp.en_name).ll().scale(0,1)
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self.add_layout_pin(text=self.en_name,
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self.add_layout_pin(text=self.en_name,
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layer="m1",
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layer=sclk.layer,
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offset=sclk_offset,
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offset=sclk_offset,
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width=self.width,
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width=self.width,
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height=drc("minwidth_m1"))
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height=drc("minwidth_" + sclk.layer))
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def input_load(self):
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def input_load(self):
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return self.amp.input_load()
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return self.amp.input_load()
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@ -145,20 +145,20 @@ class write_driver_array(design.design):
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inst = self.driver_insts[i]
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inst = self.driver_insts[i]
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din_pin = inst.get_pin(inst.mod.din_name)
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din_pin = inst.get_pin(inst.mod.din_name)
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer="m2",
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layer=din_pin.layer,
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offset=din_pin.ll(),
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offset=din_pin.ll(),
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width=din_pin.width(),
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width=din_pin.width(),
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height=din_pin.height())
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height=din_pin.height())
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer="m2",
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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width=bl_pin.width(),
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height=bl_pin.height())
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height=bl_pin.height())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer="m2",
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layer=br_pin.layer,
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offset=br_pin.ll(),
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offset=br_pin.ll(),
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width=br_pin.width(),
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width=br_pin.width(),
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height=br_pin.height())
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height=br_pin.height())
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@ -22,6 +22,10 @@ class sense_amp_test(openram_test):
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globals.init_openram(config_file)
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globals.init_openram(config_file)
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# check sense amp array for single port
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# check sense amp array for single port
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
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self.local_check(a)
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
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debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
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a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=2)
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self.local_check(a)
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self.local_check(a)
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