mirror of https://github.com/VLSIDA/OpenRAM.git
Fix precharge vdd route layer
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@ -105,17 +105,14 @@ class precharge(design.design):
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# center of vdd rail
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# center of vdd rail
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pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
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pmos_vdd_pos = vector(pmos_pin.cx(), vdd_position.y)
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self.add_path(self.bitline_layer, [pmos_pin.center(), pmos_vdd_pos])
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self.add_path(self.en_layer, [pmos_pin.center(), pmos_vdd_pos])
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self.add_via_stack_center(from_layer=self.bitline_layer,
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to_layer=self.en_layer,
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offset=pmos_vdd_pos)
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self.add_power_pin("vdd",
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self.add_power_pin("vdd",
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self.well_contact_pos,
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self.well_contact_pos,
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directions=("V", "V"))
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directions=("V", "V"))
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self.add_via_stack_center(from_layer=pmos_pin.layer,
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self.add_via_stack_center(from_layer=pmos_pin.layer,
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to_layer=self.bitline_layer,
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to_layer=self.en_layer,
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offset=pmos_pin.center(),
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offset=pmos_pin.center(),
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directions=("V", "V"))
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directions=("V", "V"))
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