mirror of https://github.com/VLSIDA/OpenRAM.git
Re-add simplified power pins on edges
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@ -135,19 +135,9 @@ class write_mask_and_array(design.design):
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width=wmask_out_pin.width(),
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width=wmask_out_pin.width(),
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height=wmask_out_pin.height())
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height=wmask_out_pin.height())
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for n in ["vdd", "gnd"]:
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self.add_power_pin("gnd", vector(supply_pin.width()+i*self.wmask_en_len,0))
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pin_list = self.and2_insts[i].get_pins(n)
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self.add_power_pin("vdd", vector(supply_pin.width()+i*self.wmask_en_len,self.height))
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for pin in pin_list:
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pin_pos = pin.lc()
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# Add the M1->M2 stack
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=pin_pos)
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# Add the M2->M3 stack
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="metal3",
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offset=pin_pos)
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def en_width(self, pin):
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def en_width(self, pin):
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