Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.

This commit is contained in:
Hunter Nichols
2018-11-01 12:29:49 -07:00
parent 9321f0461b
commit b00fc040a3
4 changed files with 94 additions and 8 deletions
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