Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.

compiler/tests/14_replica_bitline_test.py

@@ -24,6 +24,26 @@ class replica_bitline_test(openram_test):
         debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
         a = replica_bitline.replica_bitline(stages,fanout,rows)
         self.local_check(a)
+        #debug.error("Exiting...", 1)
+        
+        stages=8
+        rows=100
+        debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
+        a = replica_bitline.replica_bitline(stages,fanout,rows)
+        self.local_check(a)
+        
+        #check replica bitline in handmade multi-port 1rw+1r cell
+        OPTS.bitcell = "bitcell_1rw_1r"
+        OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.num_r_ports = 1
+        stages=4
+        fanout=4
+        rows=13
+        debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
+        a = replica_bitline.replica_bitline(stages,fanout,rows)
+        self.local_check(a)
 
         stages=8
         rows=100
@@ -31,7 +51,7 @@ class replica_bitline_test(openram_test):
         a = replica_bitline.replica_bitline(stages,fanout,rows)
         self.local_check(a)
         
-        # check replica bitline in multi-port
+        # check replica bitline in pbitcell multi-port
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell = "replica_pbitcell"
         OPTS.num_rw_ports = 1
@@ -61,7 +81,7 @@ class replica_bitline_test(openram_test):
         debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
         a = replica_bitline.replica_bitline(stages,fanout,rows)
         self.local_check(a)
-
+        
         stages=8
         rows=100
         debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))